Abstract: A method for detecting the thicknesses of coating layers of nuclear fuel particles, comprising: collecting a surface image of a sample to be tested under a first amplification factor (S310); determining a testable particle in the surface image (S320); collecting a cross section image of the testable particle under a second amplification factor, wherein the second amplification factor is greater than the first amplification factor (S330); and determining the center of the testable particle in the cross section image and profile lines of all coating layers, and determining the thickness of each coating layer according to the center and the profile lines of each coating layer (S340). Also provided is a device for detecting the thicknesses of coating layers of the nuclear fuel particles.

Abstract: A request to program host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination is made, in view of the received request, whether the host data is valid data or invalid data. In response to a determination that the host data is invalid data, updated redundancy metadata associated with the host data is generated. The updated redundancy metadata indicates that the host data is invalid data. The host data and the updated redundancy metadata is programmed to the memory device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor fin. The semiconductor structure also includes a first nanowire vertically overlapping a top surface of the semiconductor fin, a second nanowire vertically overlapping the first nanowire, and a third nanowire vertically overlapping the second nanowire. The semiconductor structure further includes a gate wrapping around the first nanowire, the second nanowire, and the third nanowire. A first portion of the gate vertically sandwiched between the first nanowire and the second nanowire is greater than a second portion of the gate vertically sandwiched between the second nanowire and the third nanowire.

Abstract: Provided in the present application is a negative electrode plate comprising a current collector and a coating applied to at least one surface of the current collector, the coating comprising a negative electrode active material and a metal powder, wherein the electrode potential of the metal powder in the coating relative to lithium may be between 1.6 and 3.5 V, the negative electrode active material may be a silicon-based material, and relative to the total weight of the silicon-based material and the metal powder, the proportion by weight of the metal powder may be 5 to 20% and the proportion by weight of the silicon-based material may be 80 to 95%.

Abstract: The present invention belongs to the bioengineering field, and relates to a method for fermentation production of L-theanine by using an Escherichia coli genetically engineered bacterium. The engineered bacterium is obtained by serving a strain as an original strain, wherein the strain is obtained after performing a single copy of T7RNAP, a dual copy of gmas, xylR knockout, and sucCD knockout on an Escherichia coli W3110 genome, and by integrating genes xfp, pta, acs, gltA, and ppc, and knocking out ackA on the genome. The present invention has a high yield, and stable production performance; after 20-25 h, L-theanine has a titer of 75-80 g/L, and the yield is up to 52-55%. The fermentation broth is purified by membrane separation in combination with a cation-anion resin series technique. Moreover, the one-step crystallization yield is 72.3% and the L-theanine final product has a purity of 99%.

Abstract: A method for fabrication of a 3D printed part with high through-plane thermal conductivity is provided, where pure polymer particles and a carbon-based filler for heat conduction are subjected to milling and mixing in the mechanochemical reactor disclosed in Chinese patent ZL 95111258.9 under the controlled milling conditions including milling pan surface temperature, milling pan pressure, and number of milling cycles; then a resulting mixture is extruded to obtain 3D printing filaments; and finally, the 3D printing filaments are used to fabricate the 3D printed part with high through-plane thermal conductivity through fused deposition modeling (FDM) 3D printing. The fabrication method can realize the fabrication of a 3D printed part with high through-plane thermal conductivity through the FDM 3D printing technology, features simple process, continuous production, etc., and is suitable for the industrial production of thermally-conductive parts with complex structures.

Abstract: A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.

Abstract: The present disclosure provides an audio data processing circuit and an audio data processing method. The audio data processing circuit includes a word select interface, a clock signal interface and an audio data interface. The word select interface is configured to receive a word select signal. The clock signal interface is configured to receive a clock signal, and generating an audio data interface signal according to a number of clocks of the clock signal in one period of the word select signal. The audio data interface is configured to transmit the audio data to a processing unit through a first transmission protocol or a second transmission protocol.

Abstract: The present invention provides a compound of formula (I) or a pharmaceutically acceptable salt thereof, pharmaceutical compositions comprising a compound of the invention, a method for manufacturing compounds of the invention and therapeutic uses thereof.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.

Abstract: A system may include a first network device. The first network device may include a first processor configured to: obtain a copy of a first message sent from an application on a User Equipment device (UE); construct a signature based on the copy of the first message; and send a second message including the signature to a second network device. The second message may request the second network device to either train a classification model or to provide a device type of the UE or an application type of the application to the first network device.

Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.

Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

Abstract: A request to program host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination is made, in view of the received request, whether the host data is valid data or invalid data. In response to a determination that the host data is invalid data, updated redundancy metadata associated with the host data is generated. The updated redundancy metadata indicates that the host data is invalid data. The host data and the updated redundancy metadata is programmed to the memory device.

Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.

Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first portion of an oxide layer around the dummy contact structure, performing a second etching process to at least partially remove the first portion of oxide layer, forming a spacer layer around the dummy contact structure, performing a second deposition process to form a second portion of the oxide layer around the spacer layer, removing the spacer layer and the dummy contract structure to leave an opening, and filling the opening with a conductive material to form a conductive plug.

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.

Abstract: First and second data are identified, such that the second data is based on a modification operation performed on the first data. First error-checking data comprising a Cyclic Redundancy Check (CRC) value of the first data is identified. Incremental error-checking data is generated based on a difference between the first data and the second data. Updated first error-checking data is generated based on a combination of the first error-checking data and the incremental error-checking data. The updated first error-checking data is compared to second error-checking data generated from a CRC value of the second data to determine whether the second data contains an error.