Abstract: A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.

Abstract: A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a semiconductor-metal compound layer formed so as to cover the entire upper surface of the interconnection layer except for a bottom portion of the first pillar-shaped semiconductor layer, a first gate insulating film surrounding the first pillar-shaped semiconductor layer, a first gate electrode surrounding the first gate insulating film, and a first gate line connected to the first gate electrode.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. S stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.

Abstract: An SRAM includes three Si pillars. In upper parts of the Si pillars, a first load P-channel, a first driver N-channel, and a first selection N-channel are formed, and in lower parts of the Si pillars, a second load P-channel, a second driver N-channel, and a second selection N-channel are formed. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the second load P-channel and the second driver N-channel. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the first load P-channel and the first driver N-channel. Gates surrounding the first and second selection N-channels are connected to a word-line terminal.

Abstract: A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing hydrogen fluoride ions is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched and an opening is thereby formed on the outer periphery of the Si pillar.

Abstract: A pillar-shaped semiconductor memory device includes an i-layer substrate and silicon pillars formed on the i-layer substrate. Tunnel insulating layers, a data charge storage insulating layer, an interlayer insulating layer, and gas layers are formed so as to surround outer peripheries of the silicon pillars. Word lines that are separated from each other by interlayer insulating layers are formed so as to surround outer peripheries of the gas layers in a direction perpendicular to an upper surface of the i-layer substrate.

Abstract: A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

Abstract: An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated structure including two sets each including a Ni film, a poly-Si layer containing donor or acceptor impurity atoms, and a SiO2 layer is formed so as to surround the opening. A heat treatment is carried out to form silicide from the poly-Si layers and this silicide formation causes the resultant NiSi layers to protrude and come into contact with the side surface of the Si pillar. The donor or acceptor impurity atoms diffuse from the NiSi layers into the Si pillar to thereby form an N+ region and a P+ region serving as a source or a drain of SGTs.

Abstract: The scissor-type conveying device moves vertically in an optical disk library device and includes a scissor-type conveying device including a slave table including a first driving mechanism used for horizontal movement of an optical-disk handling section that handles optical disks, a base table including a second driving mechanism for lifting and lowering movement, a link mechanism including a plurality of scissors links that couple the slave table and the base table and pins that combine crossing points of the scissors links crossing in an X shape, an opening and closing action of the scissors links being realized by the second driving mechanism, and a movable fixing mechanism that fixes the slave table and the base table to inner wall surfaces defining moving spaces of the slave table and the base table or releases the slave table and the base table from a fixed state to the inner wall surfaces.

Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.

Abstract: A pillar-shaped semiconductor memory device includes Si pillars arranged in at least two rows; a tunnel insulating layer; a data charge storage insulating layer; first, second, and third interlayer insulating layers; and first and second conductor layers, all of which surround outer peripheries of the Si pillars, the first and second conductor layers being located at the same height in a perpendicular direction. A row of the semiconductor pillars is interposed between the first and second conductor layers of Si pillars arranged in an X direction. Shapes of the first and second conductor layers facing the semiconductor pillars are circular arcs. Adjacent circular arcs of the first conductor layer are in contact with each other, and adjacent circular arcs of the second conductor layer are in contact with each other. A pitch length of the Si pillars in the X direction is smaller than that in a Y direction.

Abstract: A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a semiconductor-metal compound layer formed so as to cover the entire upper surface of the interconnection layer except for a bottom portion of the first pillar-shaped semiconductor layer, a first gate insulating film surrounding the first pillar-shaped semiconductor layer, a first gate electrode surrounding the first gate insulating film, and a first gate line connected to the first gate electrode.

Abstract: A SiO2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO2 layer. Two stacks of layers, each stack being constituted by a Ni layer, a poly-Si layer containing a donor or acceptor impurity atom, and a SiO2 layer, are formed in a peripheral portion of the opening, and heat treatment is performed to silicidate the poly-Si layers into NiSi layers. The NiSi layers protrude and come into contact with the side surface of the Si pillar by silicidation, and a donor or acceptor impurity atom diffuses from the NiSi layers into the Si pillar. Thus an N+ region and a P+ region serving as a source and a drain of surrounding gate MOS transistors are respectively formed above and under the SiO2 layer.

Abstract: A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.

Abstract: A pillar-shaped semiconductor memory device includes a silicon pillar, and a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, and a first conductor layer, which surround an outer periphery of the silicon pillar in that order, and a second interlayer insulating layer that is in contact with an upper surface or a lower surface of the first conductor layer. A side surface of the second interlayer insulating layer facing a side surface of the first interlayer insulating layer is separated from the side surface of the first interlayer insulating layer with a distance therebetween, the distance being larger than a distance from the side surface of the first interlayer insulating layer to a side surface of the first conductor layer facing the side surface of the first interlayer insulating layer.

Abstract: A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing moisture is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched with hydrogen fluoride ions generated from hydrogen fluoride gas supplied to the hydrogen fluoride ion diffusion layer and an opening is thereby formed on the outer periphery of the Si pillar.