Abstract: In a method for producing a semiconductor device, Si pillars that include i-layers, N+ regions that serve as lower impurity regions, N+ regions and a P+ region that serve as upper impurity regions, and i-layers are formed by using SiO2 layers as an etching mask. Thus, surrounding gate MOS transistors (SGTs) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the SGTs formed in upper portions and lower portions of the Si pillars.

Abstract: Isotropic etching is conducted by using SiN layers that are disposed on i-layers having an island structure on an i-layer substrate and have the same rectangular shape in a plan view as the i-layers. As a result, SiO2 layers each having a circular shape in a plan view are formed. Then the SiN layers are removed and the i-layers are etched by using the SiO2 layers as a mask to form Si pillars. Then surrounding gate MOS transistors are formed in the Si pillars.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.

Abstract: A semiconductor device includes a first planar silicon layer, first and second pillar-shaped silicon layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer.

Abstract: In a method for producing a semiconductor device, Si pillars that include i-layers, N+ regions that serve as lower impurity regions, N+ regions and a P+ region that serve as upper impurity regions, and i-layers are formed by using SiO2 layers as an etching mask. Thus, surrounding gate MOS transistors (SGTs) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the SGTs formed in upper portions and lower portions of the Si pillars.

Abstract: In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P+ regions connected to a pixel selection line conductive layer are formed on top layer portions of upper ends of the island-shaped semiconductors so as to adjoin the N regions and the P regions. In the P+ regions, a first P+ region has a thickness less than a second P+ region, and the second P+ region has a thickness less than a third P+ region.

Abstract: In an optical disc drive, a degradation of traveling performance of an optical pickup under hard acceleration or hard deceleration in a random access operation or the like results in a degradation of recording/reproducing performance. Groove structure is provided between two gears of a guide feed provided in an optical pickup, and the groove forms bending structure. Thus, the engagement state between a screw gear and the gears of the guide feed is stabilized. This makes it possible to prevent tooth jumping and step-out from occurring in the gears during the traveling of the optical pickup, achieving stable traveling. In consequence, the recoding/reproducing performance of the optical disc drive can be improved.

Abstract: A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.

Abstract: There is provided a solid-state imaging device in which a plurality of pixels is two-dimensionally arranged in a pixel region. Each of the pixels is formed in an island-shaped semiconductor. In this island-shaped semiconductor, a signal line N+ region and a P region are formed from the bottom. On an upper side surface of this P region, an N region and a P+ region are formed from an inner side of the island-shaped semiconductor. Above the P region, a P+ region is formed. By setting the P+ region and the P+ region to have a low-level voltage and setting the signal line N+ region to have a high-level voltage that is higher than the low-level voltage, signal charges accumulated in the N region are discharged to the signal line N+ region via the P region.

Abstract: In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P+ regions connected to a pixel selection line conductive layer are formed on top layer portions of upper ends of the island-shaped semiconductors so as to adjoin the N regions and the P regions. In the P+ regions, a first P+ region has a thickness less than a second P+ region, and the second P+ region has a thickness less than a third P+ region.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

Abstract: A method for producing a semiconductor device includes the steps of forming first and second pillar-shaped semiconductors on a substrate at the same time so as to have the same height; forming a first semiconductor layer by doping a bottom region of the first pillar-shaped semiconductor with a donor or acceptor impurity to connect the first semiconductor layer to the second pillar-shaped semiconductor; forming a circuit element including an upper semiconductor region formed by doping an upper region of the first pillar-shaped semiconductor with a donor or acceptor impurity; forming a first conductor layer in the second pillar-shaped semiconductor; forming first and second contact holes that are respectively connected to the first and second pillar-shaped semiconductors; and forming a wiring metal layer that is connected to the upper semiconductor region and the first conductor layer through the first and second contact holes, respectively.

Abstract: A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.

Abstract: A semiconductor device includes a first planar silicon layer, first and second pillar-shaped silicon layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer.

Abstract: Each pixel of a solid state imaging device comprises a first semiconductor layer formed on a substrate, having a first-conductive type; a second semiconductor layer formed thereon, having a second-conductivity type; a third semiconductor layer formed in the upper side of the second semiconductor layer, having the first-conductivity type; a fourth semiconductor layer formed in the outer side of the third semiconductor layer, having the second-conductivity type; a gate conductor layer formed on the lower side of the second semiconductor layer via an insulating film; and a fifth semiconductor layer formed on the top surfaces of the second semiconductor layer and third semiconductor layer, having the second-conductivity type, wherein the fifth semiconductor layer and fourth semiconductor layer are connected to each other, and at least the third semiconductor layer, upper region of the second semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer are formed in an island.