Abstract: A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.

Abstract: In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.

Abstract: A method for producing a pillar-shaped semiconductor device includes, forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate. A gate insulating layer and gate conductor layer are formed surrounding each of the pillars and impurity regions are formed in each pillar. The gate conductor layer is selectively processed to form gate conductors around the pillars and to interconnect the gate conductors.

Abstract: An SRAM includes two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and a drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.

Abstract: A method for producing a pillar-shaped semiconductor device includes steps of forming, on the side surface of an N+ layer (38b) of the top portion of a Si pillar (6b) and the side surface of the top portion of a W layer (43a), ring-shaped SiO2 layers and an AlO layer (51) in outer peripheral portions surrounding the ring-shaped SiO2 layers; etching the ring-shaped SiO2 layers through the AlO layer serving as a mask, to form ring-shaped contact holes; and filling the contact holes with W layers (52a, 52b), to form ring-shaped W layers (52a, 52d) being in contact with the side surface of the N+ layer (38b) and the side surface of the top portion of the W layer (43a), and having constant widths in plan view.

Abstract: A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.

Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.

Abstract: The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate (1a), a Si pillar (4a) and an impurity region (12a) located in a lower portion of the Si pillar (4a) and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region (12a) in plan view, a step of forming a SiO2 layer (11a) on the SiO2 layer such that the SiO2 layer (11a) surrounds the Si pillar (4a) in plan view, a step of forming a resist layer (13) that is partly connected to the SiO2 layer (11a) in plan view, and a step of forming a SiO2 layer (8a) by etching the SiO2 layer below the SiO2 layer (11a) and the resist layer (13) using the SiO2 layer (11a) and the resist layer (13) as masks.

Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.

Abstract: An SRAM includes three Si pillars. In upper parts of the Si pillars, a first load P-channel, a first driver N-channel, and a first selection N-channel are formed, and in lower parts of the Si pillars, a second load P-channel, a second driver N-channel, and a second selection N-channel are formed. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the second load P-channel and the second driver N-channel. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the first load P-channel and the first driver N-channel. Gates surrounding the first and second selection N-channels are connected to a word-line terminal.

Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. S stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.

Abstract: A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing hydrogen fluoride ions is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched and an opening is thereby formed on the outer periphery of the Si pillar.

Abstract: The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate (1a), a Si pillar (4a) and an impurity region (12a) located in a lower portion of the Si pillar (4a) and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region (12a) in plan view, a step of forming a SiO2 layer (11a) on the SiO2 layer such that the SiO2 layer (11a) surrounds the Si pillar (4a) in plan view, a step of forming a resist layer (13) that is partly connected to the SiO2 layer (11a) in plan view, and a step of forming a SiO2 layer (8a) by etching the SiO2 layer below the SiO2 layer (11a) and the resist layer (13) using the SiO2 layer (11a) and the resist layer (13) as masks.

Abstract: A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

Abstract: An SGT is formed in Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

Abstract: An SRAM includes two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and a drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.

Abstract: A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.

Abstract: A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a semiconductor-metal compound layer formed so as to cover the entire upper surface of the interconnection layer except for a bottom portion of the first pillar-shaped semiconductor layer, a first gate insulating film surrounding the first pillar-shaped semiconductor layer, a first gate electrode surrounding the first gate insulating film, and a first gate line connected to the first gate electrode.