Abstract: Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Abstract: A vision inspection and correction method, which uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in or out, shift, focus, diverge, and rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted. Then, the binocular images are aligned, and the inspector will implant the correction parameters during the image adjustment process into 3D projectors, VR (virtual reality), AR (augmented reality device), MR hybrid reality device and other equipment to adjust the binocular digital image parameters, so users have, or can provide to a lens maker, personalized adjustment for comfortable images of both eyes.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Abstract: Disclosed is a pharmaceutical nanoparticle containing a core and a shell coating the core. The core contains (3-{4-[2-({4-[3-(3-cyclohexylamino-propylamino)-propyl]-oxazol-2-ylmethyl}-amino)-6-methyl-pyrimidin-4-ylamino]-piperidin-1-yl}-3-oxo-propylamino)-acetic acid or a salt thereof, 1,2-dioleoyl-sn-glycero-3-phosphate, and an anionic polymer. The shell contains a lipid. Also disclosed is a method for preparing such as pharmaceutical nanoparticle. Further provided are a liposome containing a lipid bilayer enclosing an aqueous core and its preparation method.

Abstract: An optical fingerprint imaging device, including a substrate, an imaging module, at least one light emitting element, a light shielding element, a case, and a pressing substrate, is provided. The light shielding element is disposed between the imaging module and the light emitting element. The optical fingerprint imaging device satisfies conditional expressions, h?H?h+(R/tan(?/2)) and Ravg<S<5Ravg, where h is a height from a field angle origin of the imaging module to the substrate, H is a height of the light shielding element at a measurement position, R is a distance from a center of the imaging module to the measurement position, ? is an angle of a field angle of the imaging module, Ravg is an average value of distances from the center to measurement positions of the light shielding element, and S is a distance from the center to a center of the light emitting element.

Abstract: An endoscope imager includes a system-in-package and a specularly reflective surface. The system-in-package includes (a) a camera module having an imaging lens with an optical axis and (b) an illumination unit. The system-in-package includes (a) a camera module having an imaging lens with an optical axis and (b) an illumination unit configured to emit illumination propagating in a direction away from the imaging lens, the direction having a component parallel to the optical axis. The specularly reflective surface faces the imaging lens and forming an oblique angle with the optical axis, to deflect the illumination toward a scene and deflect light from the scene toward the camera module.

Abstract: The present invention provides a compound having the structure: wherein R1, R2, R3, R4, and R5 are each independently H, halogen, CF3 or C1-C4 alkyl, wherein two or more of R1, R2, R3, R4, or R5 are other than H; R6 is H, OH, or halogen; and B is a substituted or unsubstituted heterobicycle, wherein when R1 is CF3, R2 is H, R3 is F, R4 is H, and R5 is H, or R1 is H, R2 is CF3, R3 is H, R4 is CF3, and R5 is H, or R1 is Cl, R2 is H, R3 is H, R4 is F, and R5 is H, or R1 is CF3, R2 is H, R3 is F, R4 is H, and R5 is H, or R1 is CF3, R2 is F, R3 is H, R4 is H, and R5 is H, or R1 is Cl, R2 is F, R3 is H, R4 is H, and R5 is H, then B is other than or a pharmaceutically acceptable salt thereof.

Abstract: A pyrimidine ring compound represented by formula (III), or a pharmaceutically acceptable salt thereof, and an application thereof in preparation of a medication for treating related diseases.

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

Abstract: The present disclosure relates to novel compounds useful as inhibitors of ATR kinase, as well as pharmaceutical compositions comprising these compounds and methods of treatment by administration of these compounds or the pharmaceutical compositions.

Abstract: The present application provides a method for manufacturing a memory device having a word line (WL) with dual conductive materials. The method includes steps of providing a semiconductor substrate with an active area defined adjacent to a surface of the semiconductor substrate; forming a recess extending from the surface into the semiconductor substrate; disposing a first insulating layer conformal to the recess; disposing a first conductive material within the recess and surrounded by the first insulating layer; removing a portion of the first conductive material to form a first conductive member; disposing a second insulating layer within the recess and conformal to the first insulating layer and the first conductive member; and disposing a second conductive material within the recess and surrounded by the second insulating layer to form a second conductive member adjacent to the first conductive member.

Abstract: The present application provides a memory device having a word line (WL) with dual conductive materials. The memory device includes a semiconductor substrate with an active area defined adjacent to a surface of the semiconductor substrate, wherein the semiconductor substrate includes a recess extending from the surface into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes a first insulating layer disposed within and conformal to the recess, a first conductive member surrounded by the first insulating layer and disposed within the recess, a second insulating layer disposed conformal to the first insulating layer and the first conductive member, and a second conductive member disposed adjacent to the first conductive member and surrounded by the second insulating layer.

Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Abstract: The application discloses a touch display device including a touch display panel and a light source structure. The touch display panel has a first side used to display and a second d side opposite to the first side. The touch display panel includes a color filter substrate and an array substrate. The color filter substrate includes a color filter base having a first surface. The array substrate includes an array base having a second surface. At least one touch wiring layer is arranged on one of the first surface and the second surface. A light source structure arranged on a display side of the touch display panel is used to emit light to the touch display panel.

Abstract: The present disclosure relates a method of forming an integrated chip. The method includes forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate, and forming a second ILD layer over the first ILD layer. The second ILD layer is patterned to form an interconnect opening that exposes the first interconnect. A blocking layer is formed onto the first interconnect. A barrier layer is formed within the interconnect opening and the blocking layer is removed to expose the first interconnect. A second interconnect is formed within the interconnect opening.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Abstract: Disclosed are an atomizing assembly convenient to assemble automatically, an atomization device and a manufacturing method thereof. The atomizing assembly includes a heating assembly, a cover and a seat. The heating assembly includes a heating member including a heating portion and an electrical connecting portion. The cover is provided with an electrode connecting hole open longitudinally and configured for inserting an electrode. The electrical connecting portion extends into an inlet of the electrode connecting hole. The atomizing device includes a housing and the atomizing assembly. The manufacturing method of the atomizing assembly includes: assembling the heating assembly, the cover and the seat; inserting the electrode into the electrode connecting hole, and the electrode bending the electrical connecting portion into the electrode connecting hole.

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.