Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240310544
    Abstract: A method for imaging a formation of a subsurface includes receiving input data d related to the subsurface, generating synthetic data u related to the subsurface, by applying an implicit finite-difference approach to a reflectivity model r, updating a velocity model V based on the input data d and the synthetic data u, and generating an image of the formation in the subsurface based on the updated velocity model, wherein the formation is used to locate natural resources.
    Type: Application
    Filed: November 17, 2023
    Publication date: September 19, 2024
    Inventors: Kawin NIMSAILA, Gang LIU, Zedong WU, Zhigang ZHANG, Ping WANG
  • Publication number: 20240315095
    Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.
    Type: Application
    Filed: April 18, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Yi-Feng Hsu
  • Patent number: 12094903
    Abstract: Microstructure enhanced photodector arrangements uses a CMOS image sensor (CIS) wafer of crystalline Si and a CMOS Logic Processor (CLP) wafer stacked on each other for electrical interaction. The wafers can be fabricated separately and stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays are enhanced with microstructure holes. Avalanche photodiodes, single photon avalanche photodiodes and phototransistors can be laterally and/or vertically doped. Photodetectors/photosensors can have slanted sidewalls for improved optical confinement and reduced crosstalk.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 17, 2024
    Assignee: W&W SENS DEVICES, INC
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 12095088
    Abstract: A method of preparing a lithium-ion battery electrode, S1, preparing a carbon nanotube raw material; S2, providing an electrode active material and a solvent; S3, mixing the carbon nanotube raw material and the electrode active material with the solvent to form a mixture, and stirring the mixture to form an electrode mixture; and S4, spraying the electrode mixture on a substrate to form an electrode layer, and removing the substrate and drying the electrode layer to form the lithium-ion battery electrode.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: September 17, 2024
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Han Fang, Jia-Ping Wang, Shou-Shan Fan
  • Patent number: 12084277
    Abstract: The invention relates to a sterilization and deodorization waste bin, in particular to a sterilization and deodorization waste bin with a dual-band ultraviolet tube, which comprises an isolation cavity formed in an inner side of a lid and a dual-band ultraviolet tube mounted in the isolation cavity and capable of generating ultraviolet light waves for direct sterilization and ultraviolet light waves for ozone sterilization. The isolation cavity comprises a reflector and transparent quartz glass, an open surface of the reflector faces an inner cavity of the bin body, and the transparent quartz glass matches the open surface of the reflector in shape and size and covers an opening of the reflector through a silicone seal ring.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 10, 2024
    Assignees: FUJIAN NASHIDA ELECTRONIC INCORPORATED COMPANY, NINE STARS GROUP, (USA) INC
    Inventors: Shi ping Wang, Jiang qun Chen, You xi Luo, Zhou Lin
  • Patent number: 12087775
    Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Gang Chen, Bo-Cyuan Lu, Tai-Chun Huang, Chi On Chui, Chieh-Ping Wang
  • Patent number: 12087871
    Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: September 10, 2024
    Assignee: W&W Sens Devices, Inc.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 12087355
    Abstract: An adaptive control circuit of SRAM (Static Random Access Memory) includes a switch circuit, a forward diode-connected transistor, a backward diode-connected transistor, and a first delay circuit. The switch circuit is supplied by a supply voltage, and is coupled to a first node. The backward diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: September 10, 2024
    Assignee: MEDIATEK INC.
    Inventor: Dao-Ping Wang
  • Publication number: 20240295516
    Abstract: According to one embodiment, a sensor includes an element portion including a first base and a first element. The first element includes, a first fixed member fixed to the first base, a first resistance connecting member supported by the first fixed member, a first conductive connecting member supported by the first fixed member, and a first film portion supported by the first resistance connecting member and the first conductive connecting member. A first gap is provided between the first base and the first film portion. The first film portion includes a first resistance layer and a first conductive layer. The first resistance connecting member includes a first resistance wiring electrically connected to the first resistance layer. The first conductive connecting member includes a first conductive wiring electrically connected to the first conductive layer.
    Type: Application
    Filed: July 19, 2023
    Publication date: September 5, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke AKIMOTO, Akira FUJIMOTO, Yoshihiko KURUI, Ping WANG, Hiroaki YAMAZAKI
  • Publication number: 20240295514
    Abstract: According to one embodiment, a sensor includes an element section including a first base and a first element. The first element includes a first fixed member fixed to the first base, a first connecting member supported by the first fixed member, and a first film portion supported by the first connecting member. A first gap is provided between the first base and the first film portion. The first film portion includes a first resistance layer, a first conductive layer, and a first conductive member provided between the first resistance layer and the first conductive layer. A potential of the first conductive member is fixed. A first electrical resistance of the first resistance layer is configured to change according to a state of a detection target around the first element.
    Type: Application
    Filed: August 29, 2023
    Publication date: September 5, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke AKIMOTO, Akira FUJIMOTO, Yoshihiko KURUI, Ping WANG, Hiroaki YAMAZAKI
  • Publication number: 20240295513
    Abstract: According to one embodiment, a sensor includes an element section including a first base and a first element. The first element includes a first fixed member fixed to the first base, a first connecting member supported by the first fixed member, and a first film portion supported by the first connecting member. A first gap is provided between the first base and the first film portion. The first film portion includes a first resistance layer, a first conductive layer, and a first conductive member. The first resistance layer does not overlap the first conductive layer in a first direction from the first base to the first fixed member. The first conductive member overlaps the first resistance layer and the first conductive layer in the first direction. A first electrical resistance of the first resistance layer changes according to a state of a detection target around the first element.
    Type: Application
    Filed: July 19, 2023
    Publication date: September 5, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke AKIMOTO, Akira FUJIMOTO, Yoshihiko KURUI, Ping WANG, Hiroaki YAMAZAKI
  • Patent number: 12080563
    Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
  • Publication number: 20240285218
    Abstract: The present disclosure provides a method and an apparatus for assessing a physiological signal quality based on an IABP device, and relates to the technical field of medical instruments. The method includes: acquiring, in the operation process of an IABP device, physiological signal of a patient treated by the IABP device, where the physiological signal include an electrocardiographic signal and/or an arterial blood pressure signal; extracting signal parameter values of the physiological signal, where the signal parameter values include: a first kurtosis, a skewness, an effective signal ratio, a second kurtosis, and a dominant frequency; performing signal quality assessment on the physiological signal based on the signal parameter values; and implementing, based on the physiological signal, intra-aortic balloon counterpulsation in response to a signal quality assessment result represents that the signal quality of the physiological signal satisfies a preset signal quality requirement.
    Type: Application
    Filed: December 6, 2023
    Publication date: August 29, 2024
    Inventors: Ping WANG, Yao XIE
  • Publication number: 20240290575
    Abstract: A semiconductor structure includes a substrate, a semiconductor detector, a peripheral circuit, and a multilayer interconnection structure. The substrate has a sensing region and a peripheral region. The semiconductor detector is on the sensing region of the substrate. The semiconductor detector includes a first detector unit, a second detector unit, and a third detector unit. Each of the first, second, third detector units includes a first transistor and a second transistor connected in series. A gate of the second transistor is a floating gate. The peripheral circuit is on the peripheral region of the substrate and is coupled to the semiconductor detector. The multilayer interconnection structure is over the substrate. A first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Ya-Chin KING, Chrong-Jung LIN, Burn-Jeng LIN, Chien-Ping WANG, Shao-Hua WANG, Chun-Lin CHANG, Li-Jui CHEN
  • Publication number: 20240290539
    Abstract: Techniques are disclosed concerning applied magnetic field synthesis and processing of iron nitride magnetic materials. Some methods concern casting a material including iron in the presence of an applied magnetic field to form a workpiece including at least one iron-based phase domain including uniaxial magnetic anisotropy, wherein the applied magnetic field has a strength of at least about 0.01 Tesla (T). Also disclosed are workpieces made by such methods, apparatus for making such workpieces and bulk materials made by such methods.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 29, 2024
    Inventors: Jian-Ping WANG, YanFeng JIANG
  • Patent number: 12073555
    Abstract: A system for inspecting a reflective surface includes a first imaging assembly configured to take a first image of the reflective surface. The first image includes depth information. The system also includes a second imaging assembly configured to take a second image of the reflective surface. The second image includes contrast information. The system further includes a processor configured to acquire the first image and the second image, estimate a depth profile of the surface based on the depth information, correlate the depth profile with the second image, and identify a feature of the reflective surface based on the correlation.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: August 27, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zerun Ma, Guangze Li, Hui-ping Wang, Yan Cai, Blair E. Carlson
  • Publication number: 20240282728
    Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
    Type: Application
    Filed: May 2, 2024
    Publication date: August 22, 2024
    Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Publication number: 20240283075
    Abstract: A rechargeable energy storage system includes a first plurality of cells arranged in a first horizontal cell stack. Each of the first plurality of cells includes a first diameter, a first end and a second end spaced from the first end by a first distance defining a first cell axis. A second plurality of cells is arranged in a second horizontal cell stack. Each of the second plurality of cells includes a second diameter, a first end portion, and a second end portion that is spaced from the first end portion a second distance defining a second cell axis that is substantially colinear with the first cell axis. A cross beam member is disposed between the first horizontal cell stack and the second horizontal cell stack. The cross beam member absorbs heat from each of the first plurality of cells and the second plurality of cells.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 22, 2024
    Inventors: Lu Huang, Hui-ping Wang, Yangbing Zeng, Timothy M. Grewe, Blair E. Carlson, Yunzhi Xu
  • Patent number: 12069481
    Abstract: The present invention relates to an improved KNN-based 6LoWPAN network intrusion detection method. The present invention selects quantifiable security features which can reflect a self-security state of network elements of a 6LoWPAN network for training, and establishes a 6LoWPAN network feature space. The present invention assigns the weights to the features and transfers zero points, to alleviate the bias caused by large and small impact factors and simplify calculation; realizes construction and update of a state data table of network elements by extracting the feature data of network elements in real time, thus forming a normal contour updated according to the real-time state of the network in the feature space of the 6LoWPAN network based on the clustering effect of a KNN algorithm; and the present invention improves the KNN algorithm and redefines a basis for judging the invasion, to meet the requirements for 6LoWPAN network intrusion detection.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 20, 2024
    Assignee: Chongqing University of Posts and Telecommunications
    Inventors: Min Wei, Yuan Zhuang, Tao Yang, Ping Wang
  • Patent number: 12066882
    Abstract: Systems and methods for managing power consumption of device subsystems include a device which maintains one or more constraint metric tables for applications executable on the device. Each of the one or more constraint metric tables may specify respective power levels for subsystems of the device according to a respective application or an application type of the respective application. The device may determine to operate the device at a reduced power level for a first application, based on a condition for the device satisfying at least one of a thermal threshold criteria or a power threshold criteria when the device operates at full power level. The device may apply a constraint metric responsive to determining to operate at the reduced power level, to cause a subset of the plurality of subsystems to adjust a power consumption level according to a first constraint metric table corresponding to the first application.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: August 20, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Siddharth Ray, Ping Wang, Achaleshwar Sahai, Xiaodi Zhang, Neeraj Poojary, Dong Zheng, Guoqing Li, Shivank Nayak, Madhusudan Kinthada Venkata, Swaminathan Balakrishnan