Abstract: A battery enclosure to house a battery pack of an electric vehicle includes a bottom plate, a battery pack including multiple batteries or battery modules, a frame enclosure at least partially surrounding the battery pack, the frame enclosure connected with the bottom plate, the frame enclosure including at least a first side wall and a second side wall, and multiple cross members each extending between the first side wall and the second side wall. The battery enclosure includes a top plate configured to cover the multiple structural cross members and at least a portion of the battery pack. The top plate is connected with the frame enclosure and includes multiple ridges protruding from a top surface of the top plate, each ridge defining a channel extending parallel to the top surface of the top plate, and each channel configured to facilitate flow of a heat transfer medium through the channel.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

Abstract: A digital circuitry includes a reference voltage generator, a rail-to-rail low-dropout regulator and a logic circuit. The reference voltage generator generates a plurality of reference voltages. The rail-to-rail low-dropout regulator generates a plurality of control signals according to the reference voltages, and generates a plurality of driving voltages according to the control signals, wherein the driving voltages have the same variation tendency. The logic circuit operates in a voltage interval between the driving voltages.

Abstract: The disclosure describes a method that includes forming a soft magnetic material by a technique including melt spinning. The soft magnetic material includes at least one of: at least one of an ??-Fe16(NxZ1-x)2 phase domain or an ??-Fe8(NxZ1-x), where Z includes at least one of C, B, or O, and where x is a number greater than zero and less than one; or at least one of an ??-Fe16N2 phase domain or an ??-Fe8N phase domain, and at least one of an ??-Fe16Z2 phase domain or an ??-Fe8Z phase domain.

Abstract: A system comprising (1) a tuner configured to tune a radio and (2) a controller communicatively coupled to the tuner, wherein the controller is configured to (1) select a tuner code to apply to the tuner based at least in part on telemetry data indicative of a certain use-case scenario and (2) cause the tuner to tune the radio by applying the tuner code to achieve a certain state of the radio. Various other apparatuses, devices, systems, and methods are also disclosed.

Abstract: The present invention relates to a timestamp-free synchronization clock parameter tracking method based on extended Kalman filter, and belongs to the technical field of wireless sensor networks. With a first order Gauss Markov model and a clock model as a state equation, evolution processes of clock skew and instantaneous clock offset is described. Then an observation equation constituted by observation models of timestamp-free synchronization and instantaneous clock offset is established, and clock skew and instantaneous clock offset are jointly tracked by a tracking method based on extended Kalman filter to realize synchronization between a node to be synchronized and a reference clock node. The method can track two time-varying parameters simultaneously by following a network data flow without needing a dedicated synchronization frame to exchange synchronization information, which reduces energy consumption and improves synchronization precision.

Abstract: Milk fat globule-epidermal growth factor—factor VIII (MFG-E8) derived oligopeptides and pharmaceutical compositions containing the oligopeptides are provided for treating sepsis and inflammatory conditions.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.

Abstract: The present invention relates to a clock skew tracking method based on weighted observation fusion and timestamp-free interaction, and belongs to the technical field of wireless sensor networks. The method comprises performing listening synchronization by an implicit node S within an overlapping communication range between a reference node and multiple active nodes, and after multiple pairs of timestamp-free communication messages are successfully overheard, using multiple extended Kalman filtering algorithms to perform weighted fusion of multiple observed values on multiple obtained tracking results based on a scalar weighted linear minimum variance information fusion criterion, thus realizing timestamp-free relative skew fusion tracking of the implicit node.

Abstract: Systems and methods for projecting transmission occasions include a device that may determine a duration in which data is in a queue prior to transmission to an endpoint. The device may modify a phase of data capture via a sensor according to the duration. The device may capture via the sensor subsequent data according to the phase. The device may transmit the subsequent data from the queue to the endpoint.

Abstract: The present disclosure is directed to surfactants (in particular olefin sulfonates), surfactant packages, compositions derived thereof, and uses thereof in hydrocarbon recovery. Methods of making olefin sulfonate surfactants are also described.

Abstract: In general, the disclosure is directed to bulk iron-nitride materials having a polycrystalline microstructure having pores including a plurality of crystallographic grains surrounded by grain boundaries, where at least one crystallographic grain includes an iron-nitride phase including any of a body centered cubic (bcc) structure, a body centered tetragonal (bct), and a martensite structure. The disclosure further describes techniques producing a bulk iron-nitride material having a polycrystalline microstructure, including: melting an iron source to obtain a molten iron source; fast belt casting the molten iron source to obtain a cast iron source; cooling and shaping the cast iron source to obtain a bulk iron-containing material having a body-centered cubic (bcc) structure; annealing the bulk iron-containing material at an austenite transformation temperature and subsequently cooling the bulk iron-containing material; and nitriding the bulk iron-containing material to obtain the bulk iron-nitride material.

Abstract: The present disclosure is directed to surfactants (in particular olefin sulfonates), surfactant packages, compositions derived thereof, and uses thereof in hydrocarbon recovery. Methods of making olefin sulfonate surfactants are also described.

Abstract: A robotic system for forming a moldable workpiece is provided. The robotic system includes a robot, an end effector, an adjustment module, and a control module. The robot is configured to pass the workpiece through a machine. The end effector is configured to be attached to the robot and configured to grasp and release the workpiece. The end effector is adjustable to a plurality of different configurations. The adjustment module is configured to determine a change in the workpiece from (a) a first form of the workpiece prior to the passing of the workpiece through the machine to (b) a second form of the workpiece after passing of the workpiece through the machine. The control module is configured to adjust a present configuration of the end effector to a second configuration based on the change in the workpiece from (a) the first form to (b) the second form.

Abstract: A method of manufacturing a magnetoresistive random access memory, including forming a conductive plug in a substrate, forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode material layer on the substrate and the conductive plug, and performing an anisotropic etch process to pattern the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode material layer, thereby forming a magnetic memory cell on the conductive plug, wherein the anisotropic etch process overetches the conductive plug and the substrate so that a notched portion is formed on one side of an upper edge of the conductive plug, and depressed regions are formed on the substrate at two sides of the magnetic memory cell.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.