Abstract: An intelligent light supplement device, video apparatus, and an intelligent light supplement method are disclosed. The intelligent light supplement device includes a light source input module, a light source computing module, and a light source output module. The light source input module has a light sensing unit, which receives an ambient light source. The light source computing module is electrically connected to the light source input module, compares the ambient light source with a content of an illuminance comparison table to generate an illuminance control signal corresponding to an apparatus illuminance value, and/or compares the ambient light source with a content of a color temperature comparison table to generate a color temperature control signal corresponding to an apparatus color temperature value. The light source output module has a light emitting unit and drives the light emitting unit according to the illuminance control signal and/or the color temperature control signal.

Abstract: Provided is a method for determining whitening efficacy of a cosmetic raw material. In the disclosure, specific binding of melanocyte-stimulating hormone (?-MSH) to melanocortical receptor I (MC1R) on melanocytes activates adenylyl cyclase (AC). The AC could catalyze the conversion of adenosine triphosphate (ATP) into cyclic adenosine monophosphate (cAMP), causing an increased level of intracellular cAMP. Increased CAMP level activates tyrosinase through protein kinase A (PKA), thereby promoting melanin production, and then achieving the determination of a relative melanin content.

Abstract: A device may obtain, through wireless signaling from a network, a time-domain wireless-resource allocation (TWRA) pattern allocated to the device by the network and corresponding to a future time interval (TTI) for which the device has not yet decoded corresponding control information. This enables the device to conduct wireless communications during the TTI using resources allocated according to the obtained TWRA pattern, without first having to decode control information to identify the TWRA pattern. The device may obtain the TWRA pattern by obtaining an indication from the network that the TWRA pattern remains associated with future wireless communications of the device until indicated otherwise by the network, and/or by transmitting to the network an indication of preferred parameters associated with the future wireless communications and the TWRA pattern, and/or by transmitting to the network a request to have the network change from a different TWRA pattern to the TWRA pattern.

Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

Abstract: Bioactive coatings that are stabilized against inactivation by weathering are provided including a base associated with a chemically modified enzyme capable of enzymatically degrading a component of an organic stain, optionally a lipase or a lysozyme, and optionally a first polyoxyethylene present in the base and independent of the enzyme. The coatings are optionally overlayered onto a substrate to form an active coating facilitating the removal of organic stains or bacterial organic material.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: A vehicle battery includes a pouch cell configured to provide power to at least one power system of a vehicle, and multiple electrode foils stacked together at least partially within the pouch cell. Each of the multiple electrode foils includes a foil extension at an end of the electrode foil, a first group of foil extensions are connected together via a first ultrasonic weld to define a first foil extension weld portion, and a second group of foil extensions are connected together via a second ultrasonic weld to define a second foil extension weld portion.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: A fail-safe input/output device includes an input/output circuit, a comparator circuit and a resistance adjustment circuit. The input/output circuit transmits a voltage having a higher voltage level in a first supply voltage and a second supply voltage to a first node to generate a driving voltage, wherein a first target level of the first supply voltage is lower than a second target level of the second supply voltage. The comparator circuit compares the first supply voltage with the second supply voltage to generate a control signal, and selectively transmits the first supply voltage to the first node according to the control signal. The resistance adjustment circuit adjusts a resistance between the first node and a second node according to the second supply voltage, wherein the input/output circuit transmits the second supply voltage to the first node via the second node.

Abstract: A method of fabricating a heterostructure includes providing a substrate, and implementing a non-sputtered, epitaxial growth procedure at a growth temperature to form a wurtzite structure supported by the substrate. The wurtzite structure includes an alloy of a III-nitride material. The non-sputtered, epitaxial growth procedure is configured to incorporate a group IIIB element into the alloy of the III-nitride material. The growth temperature is at a level such that the wurtzite structure exhibits a breakdown field strength greater than a ferroelectric coercive field strength of the wurtzite structure.

Abstract: The present invention relates to a cross-network time synchronization method for industrial wireless network and TSN fusion, which belongs to the field of Industrial Internet, comprising the following steps: S1: conducting clock synchronization by a TSN module of a border gateway with a TSN switch of a TSN 2 in a slave clock state; S2: inside the border gateway, using the TSN module as a master clock of an industrial wireless module, and conducting clock synchronization by the industrial wireless module with the TSN module through a serial port; S3: conducting clock synchronization by a routing device in the industrial wireless network with the industrial wireless module of the border gateway through a beacon frame synchronization mode in the slave clock state, and conducting clock synchronization by the routing device as the master clock of a node device for the node device; S4: conducting clock synchronization by a terminal side conversion node in the slave clock state with the node device in the industrial

Abstract: A biodegradable film comprises from 1 wt % to 10 wt % of a first polyhydroxyalkanoate resin component, from 50 wt % to 90 wt % of a second polyhydroxyalkanoate resin component, and from 5 wt % to 48 wt % of a polybutylene adipate terephthalate resin. Specifically, the first poly(3-hydroxybutyrate-co-3-hydroxyhexanoate) resin contains a first mol % of 3-hydroxyhexanoate structural units, and the second poly(3-hydroxybutyrate-co-3-hydroxyhexanoate) resin contains a second mol % of 3-hydroxyhexanoate structural units, while the second mol % is higher than the first mol %, e.g., by 2-40 mol %, or 3-30 mol %, or 4-20 mol %.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.

Abstract: An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.