Patents by Inventor Rajeev Kumar

Rajeev Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11764190
    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: September 19, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
  • Publication number: 20230291680
    Abstract: A method may include bridging in, via a fabric, a multicast data packet from a source device to a first edge device of a plurality of edge devices and flooding the multicast data packet to the plurality of edge devices within a mutual subnetwork of the fabric. The method further includes bridging out the multicast data packet from a second edge device of the plurality of edge devices to a receiving device. The source device and the receiving device are located within the mutual subnetwork.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Applicant: Cisco Technology, Inc.
    Inventors: Rajeev Kumar, Rajagopal Venkatraman
  • Patent number: 11758708
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 12, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11758738
    Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: September 12, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Gaurav Thareja, Amrita Mathuriya
  • Patent number: 11757452
    Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: September 12, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Publication number: 20230284068
    Abstract: Aspects relate to measurement and event reporting from a distributed unit (DU) of a disaggregated base station to a central unit (CU) of the disaggregated base station. The CU can configure the DU with a measurement configuration associated with at least one value to be obtained by the DU and a reporting configuration for reporting the at least one value to the CU. The measurement reports can be sent by DU periodically or the measurement reports can be event-triggered based on the reporting configuration. In addition, the measurement reports can be UE-specific or DU/cell-specific. The measurement reports may include random access channel (RACH) reports, uplink measurement reports, radio link protocol (RLC) reports, medium access control (MAC) protocol reports, and other types of measurement or event-based reports.
    Type: Application
    Filed: April 7, 2023
    Publication date: September 7, 2023
    Inventors: Xipeng ZHU, Shankar KRISHNAN, Luis Fernando Brisson LOPES, Rajeev KUMAR
  • Publication number: 20230284456
    Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 7, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
  • Publication number: 20230284455
    Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.
    Type: Application
    Filed: August 30, 2022
    Publication date: September 7, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11751403
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: September 5, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11750197
    Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: September 5, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11748537
    Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 5, 2023
    Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11741428
    Abstract: A method for monetizing ferroelectric process development is described. In at least one embodiment, the method comprises procuring a target material based on a model driven selection which is based on charge, mass and magnetic moment, and/or mass of the atomic constituents of the target material. The method further comprises applying the target material to a fabrication process to build a ferroelectric device. The method further comprises generating a notification indicative of procurement of the target material and application of the target material. The method further comprises electronically transmitting the notification to a customer, wherein the notification includes an invoice having a line item associated with a cost of the procuring of the target material and application of the target material.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: August 29, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi, James David Clarkson, Rajeev Kumar Dokania, Debo Olaosebikan, Amrita Mathuriya
  • Patent number: 11742860
    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: August 29, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11734684
    Abstract: An authorization control network includes at least one computer server. The server(s) receives a cardholder credential and a profile modification request from a communications device, and determines an account attribute by querying a profile database with an account identifier. The server(s) rejects the modification request if the server determines from the account attribute that a limit profile associated with the account identifier is linked to a cardholder credential other than the received cardholder credential. The server(s) then receives from a POS device an authorization request that includes the account identifier and an authorization value.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: August 22, 2023
    Assignee: The Toronto-Dominion Bank
    Inventors: Rajeev Kumar Gandhi, Noemi Colmenar-Miranda, Danielle Pinnock, William Joseph McLellan, Richard Titus Szvath, Liliya Kaminskaya, Jennifer Amaral
  • Patent number: 11735245
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: August 22, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11737283
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 22, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11729995
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11729280
    Abstract: Services with policy control may be provided. A computing device may receive registration information associated with a border device. The registration information may comprise information identifying a service provided by a server associated with the border device, information identifying the border device, and policies associated with the service. Then an address for the server may be determined. Next a request may be received comprising the information identifying the service provided by the server. In response to receiving the request comprising the information identifying the service provided by the server, the address for the server, the information identifying the border device, and the policies associated with the service may be provided.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: August 15, 2023
    Assignee: Cisco Technology Inc.
    Inventors: Prakash C. Jain, Sanjay Kumar Hooda, Rajeev Kumar, Ramesh Yeevani-Srinivas
  • Patent number: 11729991
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11729697
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus of a central or management entity of an integrated access and backhaul (IAB) network may receive a report indicating one or more of a failure associated with a communication link associated with an IAB node included in the IAB network or a quality of service (QoS) associated with the communication link. The apparatus may modify a topography of the IAB network or routing within the IAB network when the report indicates the failure associated with the communication link. The apparatus may verify a QoS associated with the IAB network when the report indicates the QoS associated with the communication link. Numerous other aspects are described.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 15, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Rajeev Kumar, Karl Georg Hampel, Gavin Bernard Horn, Xipeng Zhu, Shankar Krishnan