Patents by Inventor Rajeev Kumar

Rajeev Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11694737
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: July 4, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11696451
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11694940
    Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: July 4, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
  • Patent number: 11696450
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Publication number: 20230203856
    Abstract: Door configurations having integrated mechanisms for opening and releasing for closure, with elements of these mechanisms located on or largely on the body of the door itself. In some embodiments of the disclosure, a door has a handle and two release mechanisms coupled thereto, one of which releases a lock and allows the door to open, and the other of which releases a catch and allows the door to close. The two release mechanisms are coupled to the handle such that manipulating the handle in one direction actuates one of the release mechanisms but not the other, and manipulating the handle in the other direction actuates the other release mechanism. In this manner, manipulating the handle in one direction opens the door, and manipulating the handle in the other direction closes the door.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Rajeev Kumar Singh, Stephen Paul Jones
  • Patent number: 11687548
    Abstract: Techniques are disclosed relating to the storage of backup data using a time-series data lake. For example, in various embodiments, the disclosed techniques include providing a cloud-based data lake service that maintains data for a plurality of organizations and where, for a first organization, the cloud-based data lake service maintains a time-series data lake that stores a time-series representation of data associated with the first organization. In various embodiments, the data lake service may receive backup data from a plurality of data sources associated with the first organization, generate metadata associated with the backup data, and store the backup data, along with the corresponding metadata, in the time-series data lake.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 27, 2023
    Assignee: Clumio, Inc.
    Inventors: Abdul Jabbar Abdul Rasheed, Woonho Jung, Xia Hua, Douglas Qian, Rajeev Kumar, Lawrence Chang, Karan Dhabalia, John Stewart, Rolland Miller
  • Patent number: 11688733
    Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node nl. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: June 27, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Publication number: 20230194606
    Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.
    Type: Application
    Filed: February 16, 2023
    Publication date: June 22, 2023
    Inventors: FNU Rajeev Kumar, Chandan Shantharaj
  • Publication number: 20230199692
    Abstract: Methods, systems, and devices for wireless communications are described. Some user equipment (UE) may be equipped with multiple subscriber identity modules (SIMs). A multi-SIM UE may receive a control message at a first SIM which indicates a set of sounding reference signal (SRS) resources for receiving SRS according to a first periodicity. The UE may also receive a registration message at a second SIM which includes a first parameter indicating a first set of paging occasions for receiving paging messages in accordance with a second periodicity. The UE may identify a collision in time between the one or more SRS resources and paging resources, and may transmit a registration request message to a base station. The UE may then receive a second registration message which includes a second parameter for calculating a second set of paging occasions that have a third periodicity that are non-overlapping with the SRS resources.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Priyangshu Ghosh, Akash Srivastava, Rajeev Kumar
  • Publication number: 20230187476
    Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11670352
    Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: June 6, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11664060
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: May 30, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11664371
    Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: May 30, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
  • Patent number: 11664370
    Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: May 30, 2023
    Assignee: Kepler Corpating inc.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11658664
    Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 23, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11659470
    Abstract: Fifth Generation (5G) Millimeter Wave (mmWave) cellular networks are expected to serve a large set of throughput intensive, ultra-reliable, and ultra-low latency applications. To meet these stringent requirements, while minimizing the network cost, the 3rd Generation Partnership Project has proposed a new transport architecture, where certain functional blocks can be placed closer to the network edge. In this architecture, however, blockages and shadowing in 5G mmWave cellular networks may lead to frequent handovers (HOs) causing significant performance degradation. To meet the ultra-reliable and low-latency requirements of applications and services in an environment with frequent HOs, a Fast Inter-Base Station Ring (FIBR) architecture is described, in which base stations that are in close proximity are grouped together, interconnected by a bidirectional counter-rotating buffer insertion ring network.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 23, 2023
    Assignee: New York University
    Inventors: Athanasios Koutsaftis, Rajeev Kumar, Pei Liu, Shivendra S. Panwar
  • Publication number: 20230156575
    Abstract: A method of wireless communication at a user equipment (UE), including: generating a first set of frequencies to search for signals from at least one candidate cell from which the UE may receive wireless service with respect to a first subscriber identity module (SIM); generating a second set of frequencies to search for signals from the at least one candidate cell from which the UE may receive wireless service with respect to the first SIM; scanning for one or more signals from the at least one candidate cell including tuning a first transceiver configured to operate in accordance with the first SIM to one or more of the first set frequencies; and scanning for one or more signals from the at least one candidate cell including tuning a second transceiver configured to operate in accordance with a second SIM to one or more of the second set of frequencies.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 18, 2023
    Inventors: Ansah Ahmed SHEIK, Sayak SAHA, Rajeev KUMAR
  • Patent number: 11652482
    Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 16, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11652487
    Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 16, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11653243
    Abstract: Aspects relate to measurement and event reporting from a distributed unit (DU) of a disaggregated base station to a central unit (CU) of the disaggregated base station. The CU can configure the DU with a measurement configuration associated with at least one value to be obtained by the DU and a reporting configuration for reporting the at least one value to the CU. The measurement reports can be sent by DU periodically or the measurement reports can be event-triggered based on the reporting configuration. In addition, the measurement reports can be UE-specific or DU/cell-specific. The measurement reports may include random access channel (RACH) reports, uplink measurement reports, radio link protocol (RLC) reports, medium access control (MAC) protocol reports, and other types of measurement or event-based reports.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: May 16, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xipeng Zhu, Shankar Krishnan, Luis Fernando Brisson Lopes, Rajeev Kumar