Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • III-NITRIDE ENHANCEMENT MODE TRANSISTORS WITH TUNABLE AND HIGH GATE-SOURCE VOLTAGE RATING
    Publication number: 20140042452
    Abstract: A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.
    Type: Application
    Filed: May 3, 2013
    Publication date: February 13, 2014
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Integrated lateral high voltage MOSFET
    Patent number: 8643099
    Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar, Philip L. Hower
  • Sinker with a Reduced Width
    Publication number: 20140001596
    Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Inventors: Binghua Hu, Sameer Pendharkar, Guru Mathur, Tamura Takehito
  • Drain extended CMOS with counter-doped drain extension
    Patent number: 8592900
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: November 26, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • Lateral superjunction extended drain MOS transistor
    Patent number: 8580650
    Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: November 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar
  • PROGRAMMABLE SCR FOR LDMOS ESD PROTECTION
    Publication number: 20130285137
    Abstract: A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Suhail Murtaza, Juergen Wittmann
  • Integrated Lateral High Voltage Mosfet
    Publication number: 20130277739
    Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
    Type: Application
    Filed: June 20, 2013
    Publication date: October 24, 2013
    Inventors: Marie Denison, Sameer Pendharkar, Philip L. Hower
  • High voltage transistor using diluted drain
    Patent number: 8530296
    Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
  • Integrated lateral high voltage MOSFET
    Patent number: 8476127
    Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar, Philip L. Hower
  • Thick gate oxide for LDMOS and DEMOS
    Patent number: 8470675
    Abstract: A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Sridhar, Sameer Pendharkar
  • Lateral metal oxide semiconductor drain extension design
    Patent number: 8426281
    Abstract: A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 23, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar
  • High voltage transistor using diluted drain
    Patent number: 8399924
    Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: March 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
  • GROUP III-V ENHANCEMENT MODE TRANSISTOR WITH THYRISTOR GATE
    Publication number: 20130062614
    Abstract: An apparatus includes an enhancement mode transistor having multiple Group III-V layers above a substrate and a gate above the Group III-V layers. The gate includes multiple layers of material that form at least a portion of a thyristor. The multiple layers of material may include a first p-type layer of material, an n-type layer of material on the first p-type layer, and a second p-type layer of material on the n-type layer. The multiple layers of material may also include a p-type layer of material, an n-type layer of material on the p-type layer, and a Schottky metal layer on the n-type layer. The enhancement mode transistor may represent a high electron mobility transistor (HEMT) or a heterostructure field effect transistor (HFET).
    Type: Application
    Filed: August 21, 2012
    Publication date: March 14, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Naveen Tipirneni, Sameer Pendharkar
  • INTEGRATED HIGH VOLTAGE DIVIDER
    Publication number: 20130032922
    Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 7, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER
    Publication number: 20130032863
    Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 7, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • Drain extended PMOS transistors and methods for making the same
    Patent number: 8304303
    Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer Pendharkar
  • MOS transistor with gate trench adjacent to drain extension field insulation
    Patent number: 8253193
    Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: August 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar, Binghua Hu, Taylor Rice Efland, Sridhar Seetharaman
  • Drain Extended CMOS with Counter-Doped Drain Extension
    Publication number: 20120112275
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 10, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • INTEGRATED LATERAL HIGH VOLTAGE MOSFET
    Publication number: 20120112277
    Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 10, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Philip L. Hower
  • HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI
    Publication number: 20120104497
    Abstract: An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).
    Type: Application
    Filed: October 26, 2011
    Publication date: May 3, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Philip L. Hower, Sameer Pendharkar