Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LAYER TRANSFER OF SILICON ONTO III-NITRIDE MATERIAL FOR HETEROGENOUS INTEGRATION
    Publication number: 20140329370
    Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Naveen TIPIRNENI, Sameer PENDHARKAR, Rick L. WISE
  • III-NITRIDE TRANSISTOR LAYOUT
    Publication number: 20140327011
    Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI, Jungwoo JOH
  • Programmable SCR for LDMOS ESD protection
    Patent number: 8878284
    Abstract: A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Suhail Murtaza, Juergen Wittmann
  • Integrated high voltage divider
    Patent number: 8878330
    Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • Integrated gate controlled high voltage divider
    Patent number: 8872273
    Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: October 28, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • Method of making vertical transistor with graded field plate dielectric
    Patent number: 8853029
    Abstract: An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin
  • Low-Cost CMOS Structure with Dual Gate Dielectrics and Method of Forming the CMOS Structure
    Publication number: 20140252485
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • DRIVER FOR NORMALLY ON III-NITRIDE TRANSISTORS TO GET NORMALLY-OFF FUNCTIONALITY
    Publication number: 20140252367
    Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Stepped dielectric for field plate formation
    Patent number: 8829613
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • DEEP TRENCH ISOLATION WITH TANK CONTACT GROUNDING
    Publication number: 20140183662
    Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.
    Type: Application
    Filed: December 10, 2013
    Publication date: July 3, 2014
    Inventors: Yongxi ZHANG, Eugen MINDRICELU, Sameer PENDHARKAR, Seetharaman SRIDHAR
  • LOW COST TRANSISTORS
    Publication number: 20140183631
    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.
    Type: Application
    Filed: December 10, 2013
    Publication date: July 3, 2014
    Inventors: Pinghai HAO, Sameer PENDHARKAR
  • Lateral superjunction extended drain MOS transistor
    Patent number: 8766359
    Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 1, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar
  • RESURF III-nitride HEMTs
    Patent number: 8759879
    Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Tipirneni, Sameer Pendharkar, Jungwoo Joh
  • Strained LDMOS and demos
    Patent number: 8754497
    Abstract: An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar, Umamaheswari Aghoram
  • Stacked ESD clamp with reduced variation in clamp voltage
    Patent number: 8749024
    Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Marie Denison, Yongxi Zhang
  • FAST SWITCHING IGBT WITH EMBEDDED EMITTER SHORTING CONTACTS AND METHOD FOR MAKING SAME
    Publication number: 20140070265
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE
    Publication number: 20140061859
    Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Marie Denison, Yongxi Zhang
  • JFET HAVING WIDTH DEFINED BY TRENCH ISOLATION
    Publication number: 20140062524
    Abstract: A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: BINGHUA HU, PINGHAI HAO, SAMEER PENDHARKAR
  • Drain Extended CMOS with Counter-Doped Drain Extension
    Publication number: 20140061785
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR
    Publication number: 20140061789
    Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar