Abstract: The present invention relates to a semiconductor device, a manufacturing method thereof. More specifically, this invention is related to a chemical etching method in semiconductor device separation process without using dicing or scribing. According to an example of the invention, a method for manufacturing a semiconductor device, the method comprising: forming a light emitting semiconductor device layer that emits light by current injection; and forming at least one metal layer with etch barrier plated thereon on the semiconductor device layer, wherein the at least one metal layer provides mechanical support to the semiconductor device, wherein the etch barrier is plated on the at least one metal layer in a direction that the etch barrier can prevent side wall under-cut when the street lines are separated by wet chemical etching.

Abstract: A semiconductor memory device is kept in a busy state by controlling a ready/busy pad when a detection signal is output since an external voltage is less than a reference voltage, prevents generation of an operating voltage by a pump circuit by preventing generation of a pump clock, and resets a microcontroller by preventing generation of micro clock. Accordingly, the semiconductor memory device may be prevented from malfunctioning through a series of operations when the external voltage is less than the reference voltage.

Abstract: A method for fabricating a nitride semiconductor thin film includes preparing a first nitride single crystal layer doped with an n-type impurity. A plurality of etch pits are formed in a surface of the first nitride single crystal layer by applying an etching gas thereto. A second nitride single crystal layer is grown on the first nitride single crystal layer having the etch pits formed therein.

Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: A method of fabricating a nitride semiconductor light emitting device is provided. The method includes growing a first group-III-nitride semiconductor layer on a substrate, the first group-III-nitride semiconductor layer having a top surface formed as a group-III-rich surface exhibiting a group-III-polarity and a bottom surface formed as a N-rich surface exhibiting a N-polarity. The method further includes selectively etching a N-polarity region in the top surface of the first group III nitride semiconductor layer, forming a second group III nitride semiconductor layer on the first group III nitride semiconductor layer to fill the etched N-polarity region and forming a light emitting structure including first and second conductivity type nitride semiconductor layers and an active layer on the second group III nitride semiconductor layer.

Abstract: A semiconductor memory device is kept in a busy state by controlling a ready/busy pad when a detection signal is output since an external voltage is less than a reference voltage, prevents generation of an operating voltage by a pump circuit by preventing generation of a pump clock, and resets a microcontroller by preventing generation of micro clock. Accordingly, the semiconductor memory device may be prevented from malfunctioning through a series of operations when the external voltage is less than the reference voltage.

Abstract: Provided is an apparatus and method for supplying a charge voltage to an organic photoconductor (OPC) drum. The apparatus includes a storage unit for storing first service life information of the OPC drum according to a first supplying method, and second service life information of the OPC drum according to a second supplying method, a sensor unit for measuring information about conditions surrounding the apparatus, a control unit for selecting one of the first and second supplying methods according to the measured information and determining a charge voltage corresponding to the service life information according to the selected method, and a voltage supplying unit using the selected method to supply the determined charge voltage to the OPC drum.

Abstract: There are provided a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device includes a base layer configured of a group III nitride semiconductor, a polarity modifying layer formed on a group III element polar surface of the base layer, and a light emitting laminate having a multilayer structure of the group III nitride semiconductor formed on the polarity modifying layer, an upper surface of at least one layer in the multilayer structure being formed of an N polar surface.

Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: A semiconductor light emitting device includes first and second conductivity-type semiconductor layers formed of AlxGayIn1-x-yP (0?x?1, 0?y?1, 0?x+y?1) or AlzGa1-zAs (0?z?1) and an active layer interposed between the first and second conductivity-type semiconductor layers, wherein at least one of the first and second conductivity-type semiconductor layers includes a low refractive index surface layer formed of (AlvGa1-v)0.5In0.5P (0.7?v?1) or AlwIn1-wP (0?w?1) and having depressions and protrusions.

Abstract: A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.

Abstract: A developing device to supply toner in a developer, including a development member that attaches the developer to an outer circumferential surface of the development member and supplies the toner to the image bearing member, a first regulation member including a first regulating portion that forms a first doctor gap between the outer circumferential surface of the development member and the first regulating portion, and a second regulation member disposed on an upstream side of the first regulation member in a rotational direction of the development member and includes a second regulating portion that forms a second doctor gap between the outer circumferential surface of the development member and the second regulating portion, the second doctor gaps at a central portion and both end portions in a longitudinal direction of the development member being different from each other.

Abstract: An aerosol deposition apparatus is described for reproducibly preparing standardized coupon surfaces, which mimic aerosol deposited materials in an uncontrolled environment. The dome shaped apparatus is placed over the surfaces and an aerosol is delivered to the apex of the dome. The aerosol deposited surfaces may be used as standards for evaluating decontamination methods.

Abstract: Disclosed are a substrate alignment apparatus precisely and automatically aligning a mask on a substrate by sequentially moving the substrate and the mask horizontally on a susceptor being driven up and down, a substrate processing apparatus including the same, and a substrate alignment method. The substrate alignment apparatus includes a position fixing unit protruding from an upper surface of the susceptor driven up and down in a chamber so as to form a reference line for alignment of the substrate and the mask, a horizontal transfer unit connected at outer surfaces of two sidewalls of the chamber and extended into the chamber to align the substrate and the mask according to the up and down movement of the susceptor until the substrate and the mask are stopped by the position fixing unit from horizontally moving, and a control unit adapted to control the susceptor and the horizontal transfer unit.

Abstract: An internal voltage generation circuit includes a first detection unit, a second detection unit, a control unit, and a voltage pumping unit. The first detection unit compares an internal voltage with a first reference voltage to generate a first detection signal when the first detection unit is activated in response to a first enable signal. The second detection unit compares the internal voltage with a second reference voltage to generate a second detection signal. The control unit generates the first enable signal and a second enable signal in response to the first detection signal and the second detection signal. The voltage pumping unit generates the internal voltage in response to the second enable signal.

Abstract: Provided is an apparatus and method for supplying a charge voltage to an organic photoconductor (OPC) drum. The apparatus includes a storage unit for storing first service life information of the OPC drum according to a first supplying method, and second service life information of the OPC drum according to a second supplying method, a sensor unit for measuring information about conditions surrounding the apparatus, a control unit for selecting one of the first and second supplying methods according to the measured information and determining a charge voltage corresponding to the service life information according to the selected method, and a voltage supplying unit using the selected method to supply the determined charge voltage to the OPC drum.

Abstract: A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.

Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.

Abstract: A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.