Patents by Inventor Satoshi Sakai

Satoshi Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060106757
    Abstract: An apparatus and method is provided for managing and distributing design and manufacturing information throughout a factory in order to facilitate the production of components, such as bent sheet metal components. In accordance with an aspect of the present invention, the management and distribution of critical design and manufacturing information is achieved by storing and distributing the design and manufacturing information associated with each job. By replacing the traditional paper job set-up or work sheet with, for example, an electronically stored job sheet that can be accessed instantaneously from any location in the factory, the present invention improves the overall efficiency of the factory. In addition, through the various aspects and features of the invention, the organization and accessibility of part information and stored expert knowledge is improved.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 18, 2006
    Applicant: Amada Company, Limited
    Inventors: Satoshi Sakai, Kensuke Hazama, Yoshie Hazama, Yeam-Tzuo Hwang
  • Publication number: 20060090790
    Abstract: A photoelectric conversion device is composed of a substrate, a lower electrode layer formed to cover the substrate, and a first semiconductor layer formed on the lower electrode. The lower electrode layer includes a first matrix formed of transparent conductive material, and light scattering granules embedded within the first matrix.
    Type: Application
    Filed: February 9, 2005
    Publication date: May 4, 2006
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yasuyuki Kobayashi, Satoshi Sakai, Koji Satake
  • Publication number: 20060089738
    Abstract: Analysis is performed on sheet metal products to determine characteristics (or feature vectors) of the sheet metal products. Multiple feature vectors can be obtained for each sheet metal product. Exemplary analyses include a first order moment and a second order moment. The characteristics can be compared with characteristics of other sheet metal part shapes to determine how similar the shapes are.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 27, 2006
    Applicant: Amada Company, Limited
    Inventors: Satoshi Sakai, Masanobu Ishii
  • Publication number: 20060089747
    Abstract: A method is provided for guaranteeing generation of 2D sketches based upon a 3D sheet metal part shape created by any type of sheet metal feature operation. The method includes performing a sheet metal feature operation to create the 3D sheet metal shape. The 3D sheet metal shape will have multiple flanges. Then an editable 2D sketch is created for each flange by obtaining geometric parameters of the 3D sheet metal shape, and linking the parameters with the appropriate generated sketch. The constraint parameters can include line segment lengths and angles between selected adjoining two line segments of the 3D sheet metal shape.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 27, 2006
    Applicant: Amada Company, Limited
    Inventor: Satoshi Sakai
  • Publication number: 20060079989
    Abstract: Data for a 3D sheet metal part model is stored in a file. The stored data includes features of the part and manufacturing information. When different manufacturing processes are used, different geometry can be created. The file can store multiple processes for manufacturing the part and the geometry associated with each process. Thus, when manufacturing the part, the user can view information for multiple stored processes because all of the information is stored together. In addition, both 2D and 3D data is stored for the part.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 13, 2006
    Applicant: Amada Corporation, Limited
    Inventors: Masanobu Ishii, Satoshi Sakai, Thanapandi Periasamy
  • Patent number: 7008880
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: March 7, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Patent number: 6978111
    Abstract: A cleaning apparatus for a liquid-development electrophotographic apparatus in which, after a toner image formed on a surface of an intermediate transfer member by use of a liquid developer is transferred to a printing medium, the liquid developer remaining on the intermediate transfer is removed and collected. The cleaning apparatus includes a cleaning-liquid application device for applying a cleaning liquid to the intermediate transfer member which has transferred an image to the printing medium; a bias voltage application device for applying a bias voltage opposite in polarity to charged toner particles of the developer to the intermediate transfer member; and a collection device for removing the cleaning liquid which has been applied to and the residual developer which remains on the intermediate transfer member from the intermediate transfer member without transfer of an image to the printing medium, and collecting the removed cleaning liquid and residual developer.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: December 20, 2005
    Assignee: PFU Limited
    Inventors: Isao Nagata, Satoshi Sakai, Hironaga Hongawa, Shigeharu Okano, Eri Yamanishi, Norihiro Yamasaku
  • Patent number: 6962880
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: November 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Patent number: 6962881
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: November 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20050242379
    Abstract: The objectives of the present invention are to prevent or inhibit the deterioration of optical systems that determine the longevity of an optical apparatus which delivers effects such as light transmission, diffraction, reflection, spectrum generation, and interference, and these combinations, and by so doing, decrease the frequency of maintenance operations such as window replacement and to reduce the costs for such operations. This invention is characterized by steps of creating a near vacuum zone with a presence of active energy to excite an oxidation reaction of carbon wherein the near vacuum zone faces the lighting surfaces of the optical system; generating negative ions or radicals in the near vacuum zone such as unstable chemical seeds containing oxygen atoms, such as OH radicals, OH? ions, ozone, O2? ions, O-radicals; and removing or reducing the accumulated carbon which deposits on the lighting surface, by reacting the deposited carbon with the negative ions or radicals.
    Type: Application
    Filed: April 29, 2004
    Publication date: November 3, 2005
    Inventors: Satoshi Sakai, Shigenori Tsuruga, Hideo Yamakoshi, Shizuma Kuribayashi, Minoru Danno, Hiroshi Futami, Noriko Yamazaki
  • Publication number: 20050227501
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Application
    Filed: May 19, 2005
    Publication date: October 13, 2005
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20050208731
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Application
    Filed: May 19, 2005
    Publication date: September 22, 2005
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20050205127
    Abstract: A photovoltaic device is formed by depositing at least a first transparent electrode, PIN-structured or NIP-structured microcrystalline silicon layers, a second transparent electrode, and a back electrode in sequence on an electrically insulating transparent substrate. The PIN-structured or NIP-structured microcrystalline silicon layers include a p-type silicon layer, an i-type silicon layer, and an n-type silicon layer. At least one of the first transparent electrode and the second transparent electrode is a ZnO layer doped with Ga, and the Ga concentration is 15 atomic percent or less with respect to Zn.
    Type: Application
    Filed: January 4, 2005
    Publication date: September 22, 2005
    Applicant: MITSUBISHI HEAVY INDUSTRIES LTD.
    Inventors: Toshiya Watanabe, Nobuki Yamashita, Youji Nakano, Saneyuki Goya, Satoshi Sakai, Yoshimichi Yonekura
  • Publication number: 20050186724
    Abstract: A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and suicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.
    Type: Application
    Filed: April 22, 2005
    Publication date: August 25, 2005
    Inventors: Fumio Ootsuka, Satoshi Yamamoto, Satoshi Sakai
  • Patent number: 6924237
    Abstract: A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and silicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: August 2, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Fumio Ootsuka, Satoshi Yamamoto, Satoshi Sakai
  • Patent number: 6909133
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Patent number: 6898404
    Abstract: A liquid-development electrophotographic apparatus forms on a toner-image-bearing body a plurality of color images developed by a plurality of developing units, one for each color, that use liquid toner. One or more carrier-removing units for removing excessive carrier from a toner layer that forms a toner image are disposed downstream of each developing unit and upstream of the next developing unit disposed upstream of the former developing unit with respect to a process progress direction. Each carrier-removing unit includes two or more conductive collection rollers to which a bias voltage is applied in such a direction as to press toner against the toner-image-bearing body and which is brought into contact with the toner-image-bearing body. The upstream roller is rotated in the same direction as the direction of surface movement of the toner-image-bearing body, whereas the downstream roller is rotated in the opposite direction.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: May 24, 2005
    Assignee: PFU Limited
    Inventors: Satoshi Sakai, Isao Nagata, Hironaga Hongawa, Shigeharu Okano, Eri Yamanishi, Yutaka Nakashima, Akihiko Inamoto, Tadashi Nishikawa, Norihiro Yamasaku
  • Publication number: 20050092198
    Abstract: It is the primary object of the present invention to provide a printing plate, a fabricating method thereof, a method of making a printing plate with a print image, a method of reproducing the printing plate with a print image, and a printing press that are capable of reducing the light irradiation energy required for writing an image when making a printing plate and erasing the image when reproducing the printing plate. A printing plate including a photocatalyst layer. The photocatalyst layer contains a photocatalyst TiO2 or a TiO2 compound in a surface thereof. The volume rate of an anatase-type crystal in the total crystal component of the photocatalyst TiO2 or TiO2 compound is between 0.4 and 1.0. The total volume crystallization ratio of the photocatalyst is 20% or greater.
    Type: Application
    Filed: October 18, 2004
    Publication date: May 5, 2005
    Inventors: Fumihiko Hirose, Satoshi Sakai, Hiroshi Tonegawa, Yasuharu Suda
  • Publication number: 20050077548
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 14, 2005
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Publication number: 20050045959
    Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).
    Type: Application
    Filed: November 30, 2001
    Publication date: March 3, 2005
    Inventors: Satoshi Sakai, Atsushi Hiraiwa, Satoshi Yamamoto