Patents by Inventor Shinji Takeoka
Shinji Takeoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120064148Abstract: The present invention provides pH-responsive liposomes which are capable of holding a desired substance in an acidic pH environment and releasing the desired substance in a basic pH environment. The present invention uses pH-responsive liposomes comprising, as constituent lipids thereof, a cationic amphiphilic molecule and at least one of an anionic amphiphilic molecule and a twitterionic amphiphilic molecule, wherein the liposomes, when dispersed in an aqueous medium, have a positive zeta potential in an acidic environment where the dispersion has a pH of less than 6.5 and have a negative zeta potential in a basic environment where the dispersion has a pH of 8.5 or more.Type: ApplicationFiled: March 10, 2010Publication date: March 15, 2012Applicant: BIONANOSHEETER CO., LTD.Inventors: Shinji Takeoka, Yousuke Obata, Satoru Nakagawa, Shinya Ohtsubo, Yuji Kawasaki
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Publication number: 20120049297Abstract: A gate insulating film includes an oxygen-containing insulating film and a high dielectric constant insulating film formed on the oxygen-containing insulating film and containing a first metal. The high dielectric constant insulating film further includes a second metal different from the first metal. Part of the high dielectric constant insulating film having the maximum composition ratio of the second metal is away from an interface between the high dielectric constant insulating film and the oxygen-containing insulating film and an interface between the high dielectric constant insulating film and the gate electrode. The second metal exists also in a portion of the oxygen-containing insulating film near the interface between the high dielectric constant insulating film and the oxygen-containing insulating film.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Applicant: Panasonic CorporationInventor: Shinji TAKEOKA
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Publication number: 20120034466Abstract: A thin film polymer structure obtained by the steps of: (a) causing polyfunctional molecules to adsorb to an area of an arbitrary shape in an interface between a substrate body and a liquid phase; (b) polymerizing and/or crosslinking the adsorbing polyfunctional molecules to form a polymer thin film; and (c) exfoliating the formed thin film from the substrate body.Type: ApplicationFiled: August 31, 2005Publication date: February 9, 2012Applicants: Oxygenix Co., Ltd., Shinji TAKEOKA, WASEDA UNIVERSITYInventors: Shinji Takeoka, Yosuke Okamura, Masanori Ohtsuka
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Publication number: 20110147857Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventors: Junji HIRASE, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
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Patent number: 7923764Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.Type: GrantFiled: July 20, 2009Date of Patent: April 12, 2011Assignee: Panasonic CorporationInventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
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Patent number: 7887837Abstract: The present invention provides a drug delivery material, which is a conjugate of 1) a drug-carrying molecular assembly, 2) a linker and 3) a substance that recognizes activated platelet, injury site of blood vessel and/or inflammatory tissue, and capable of efficiently delivering a drug to a desired site, during which the drug under delivery does not affect sites other than a desired site (hence, low possibility of causing side effects), which releases the drug only at the desired site without requiring an external means and allows the drug to exhibit an effect.Type: GrantFiled: January 5, 2007Date of Patent: February 15, 2011Inventors: Shinji Takeoka, Yousuke Okamura, Ippei Maekawa, Makoto Handa, Yasuo Ikeda
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Publication number: 20110006374Abstract: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Applicant: PANASONIC CORPORATIONInventors: Tokuhiko Tamaki, Naoki Kotani, Shinji Takeoka
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Patent number: 7838685Abstract: The present invention provides a novel complex lipid having a cationic functional group derived from an amino acid. Namely, the present invention provides a cationic acid amino acid type lipid represented by the following formula: wherein, R1 is a hydrocarbon group having a cationic functional group derived from an amino acid, R2 and R3 are each independently a chain hydrocarbon group, A1 and A2 are each independently a linkage group selected from the group consisting of —COO—, —OCO—, —CONH— and NHCO—, and n is an integer of 2 to 4.Type: GrantFiled: April 27, 2006Date of Patent: November 23, 2010Inventors: Shinji Takeoka, Yosuke Obata
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Publication number: 20100291672Abstract: The present invention provides a reagent for introducing a protein or gene into a cell. The reagent of the present invention is, for example, a reagent for introducing a protein or gene into a cell, which comprises a composition comprising a cationic amino acid type lipid represented by the following formula (I)-1: (wherein in formula (I)-1: L is a single bond, —CONH—, or —S—S—; M1 is —(CH2)k— or —(CH2CH2O)k— (wherein k is an integer between 0 and 14); and m1 and m2 are each independently an integer between 11 and 21 (in this regard, when providing a reagent for introducing a gene into a cell, the case where both m1 and m2 are 15 is excluded)).Type: ApplicationFiled: November 26, 2007Publication date: November 18, 2010Applicant: WASEDA UNIVERSITYInventors: Shinji Takeoka, Naoya Takeda, Hitoshi Kurumizaka, Isao Sakane, Namiko Ikegaya, Yosuke Obata, Syunsuke Saito
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Patent number: 7824987Abstract: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.Type: GrantFiled: August 11, 2009Date of Patent: November 2, 2010Assignee: Panasonic CorporationInventors: Tokuhiko Tamaki, Naoki Kotani, Shinji Takeoka
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Patent number: 7808001Abstract: An n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate 100. The p-channel MOS transistor includes a gate electrode 102a, a first offset sidewall 103a formed on side surfaces of the gate electrode 102a so as to contain fine particles 110 of group IV semiconductor therein. The n-channel MOS transistor includes a gate electrode 102b and a second offset sidewall 103b formed on side surfaces of the gate electrode 102b. After ion implantation of group IV semiconductor, heat treatment is performed to form the fine particles 110, so that a thickness of the first offset sidewall 103a can be made larger than a thickness of the second offset sidewall 103b.Type: GrantFiled: June 11, 2007Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventor: Shinji Takeoka
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Publication number: 20100237432Abstract: A semiconductor device includes a MIS transistor formed in a FET formation region of a semiconductor substrate, a silicon dioxide film formed in a trench provided in the semiconductor substrate to define the FET formation region, a gate insulating film formed over the FET formation region and the silicon dioxide film, and a gate electrode formed on the gate insulating film. The portion of the gate insulating film formed between the portion of the gate electrode located in the trench and the side surface of the semiconductor substrate contains aluminum, while the portion of the gate insulating film formed between the gate electrode and the upper surface of the semiconductor substrate does not contain aluminum.Type: ApplicationFiled: June 3, 2010Publication date: September 23, 2010Applicant: PANASONIC CORPORATIONInventors: Shinji TAKEOKA, Takashi NAKABAYASHI
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Patent number: 7786536Abstract: In a semiconductor device, a first p-type MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; a first side-wall insulating film; a first p-type source/drain region; a first contact liner film formed over the first active region; a first interlayer insulating film formed on the first contact liner film; and a first contact plug formed to reach the top surface of the first source/drain region. The first contact liner film has a slit extending, around a corner at which the side surface of the first side-wall insulating film intersects the top surface of the first active region, from the top surface of the first contact liner film toward the corner.Type: GrantFiled: November 9, 2007Date of Patent: August 31, 2010Assignee: Panasonic CorporationInventor: Shinji Takeoka
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Patent number: 7781844Abstract: A first NMIS transistor includes: a first gate dielectric film over the first active region; a first gate electrode on the first gate dielectric film; a first side-wall dielectric film on side surfaces of the first gate dielectric film and the first gate electrode; a first source/drain region in the first active region outside the first side-wall dielectric film; a first silicide layer in a top-layer portion of the first source/drain region; a second side-wall dielectric film on the first silicide layer around a corner at which the side surface of the first side-wall dielectric film meets an upper surface of the first silicide layer; and a first stressor film for exerting a tensile stress on a channel region in a gate length direction, the first stressor film covering the first gate electrode, the first side-wall dielectric film, and the second side-wall dielectric film.Type: GrantFiled: October 11, 2007Date of Patent: August 24, 2010Assignee: Panasonic CorporationInventor: Shinji Takeoka
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Publication number: 20100209458Abstract: The present invention provides an amphiphilic molecule having a plurality of zwitterionic functional groups in its hydrophilic moiety and a molecular assembly comprising the amphiphilic molecule as a constituent lipid. According to a preferred embodiment of the present invention, the molecular assembly of the present invention forms a stable vesicular structure under a physiological pH environment to carry a substance of interest in the vesicular structure, and can release the substance of interest to the outside of the vesicular structure when it is deformed under an acidic pH environment. The molecular assembly of the present invention can be used as a carrier for a drug, a probe, a nucleic acid, a protein or the like.Type: ApplicationFiled: May 16, 2008Publication date: August 19, 2010Applicants: Waseda University, JCR Pharmaceuticals Co., Ltd.Inventors: Shinji Takeoka, Yosuke Obata, Shoji Tajima, Manabu Ito, Atsushi Mizuno, Natsuko Nishiyama, Yoshito Takeuchi
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Patent number: 7732839Abstract: A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.Type: GrantFiled: September 22, 2006Date of Patent: June 8, 2010Assignee: Panasonic CorporationInventors: Akio Sebe, Naoki Kotani, Shinji Takeoka, Gen Okazaki, Junji Hirase, Kazuhiko Aida
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Publication number: 20100065910Abstract: A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate 100, a first gate insulating film 101a and a first gate electrode 102a formed on the first region of the semiconductor substrate, and first side walls (103a, 120a) formed on the side surface of the first gate electrode 102a, and the second MISFET includes a second gate insulating film 101b and a second gate electrode 102b formed on the second region of the semiconductor substrate 100, and second side walls (103b, 120b) formed on the side surface of the second gate electrode 102b. The width of the first side wall is smaller than the width of the second side wall, and the second side wall includes the second spacer 103b containing a higher concentration of hydrogen than the first spacer 103a.Type: ApplicationFiled: November 19, 2009Publication date: March 18, 2010Applicant: PANASONIC CORPORATIONInventor: Shinji TAKEOKA
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Publication number: 20100062258Abstract: A thin film polymer structure having a functional substance on the face (A surface) and reverse face (B surface) of the film, obtained by the steps of (a) causing polyfunctional molecules to adsorb to an area of an arbitrary shape in an interface between a substrate body and a liquid phase; (b) polymerizing and/or crosslinking the adsorbing polyfunctional molecules to form a polymer thin film; (c) bonding a functional substance to the A surface of the formed thin film and then (d) forming a soluble support film thereon; exfoliating the thin film and the soluble support film from the substrate body; (e) bonding to the B surface of the thin film a functional substance identical to or different from the abovementioned functional substance and then dissolving the soluble support film with a solvent. A method for preparing a thin film molecular structure having a functional substance on the face (A surface) and reverse face (B surface) of the film is offered through the above process.Type: ApplicationFiled: October 29, 2007Publication date: March 11, 2010Inventors: Shinji Takeoka, Yosuke Okamura, Toshinori Fujie, Saori Utsunomiya, Takahiro Goto
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Patent number: 7646065Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.Type: GrantFiled: October 4, 2006Date of Patent: January 12, 2010Assignee: Panasonic CorporationInventors: Naoki Kotani, Gen Okazaki, Shinji Takeoka, Junji Hirase, Akio Sebe, Kazuhiko Aida
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Publication number: 20090298255Abstract: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Applicant: Panasonic CorporationInventors: Tokuhiko TAMAKI, Naoki Kotani, Shinji Takeoka