SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a MIS transistor formed in a FET formation region of a semiconductor substrate, a silicon dioxide film formed in a trench provided in the semiconductor substrate to define the FET formation region, a gate insulating film formed over the FET formation region and the silicon dioxide film, and a gate electrode formed on the gate insulating film. The portion of the gate insulating film formed between the portion of the gate electrode located in the trench and the side surface of the semiconductor substrate contains aluminum, while the portion of the gate insulating film formed between the gate electrode and the upper surface of the semiconductor substrate does not contain aluminum.
Latest Panasonic Patents:
- METHOD FOR MANUFACTURING SUBSTRATE WITH CONDUCTIVE PATTERN ATTACHED THERETO
- CYLINDRICAL BATTERY AND MANUFACTURING METHOD FOR SAME
- NEGATIVE ELECTRODE ACTIVE MATERIAL COMPOSITE PARTICLE, METHOD FOR MANUFACTURING NEGATIVE ELECTRODE ACTIVE MATERIAL COMPOSITE PARTICLE, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY
- METHOD FOR MANUFACTURING STRETCHABLE CIRCUIT BOARD, METAL-CLAD LAMINATED SHEET, METAL FOIL WITH RESIN, STRETCHABLE CIRCUIT BOARD, AND STRETCHABLE CIRCUIT MOUNTED ARTICLE
- ANTENNA DEVICE AND ELECTRONIC EQUIPMENT
This is a continuation of PCT International Application PCT/JP2009/005216 filed on Oct. 7, 2009, which claims priority to Japanese Patent Application No. 2009-039827 filed on Feb. 23, 2009. The disclosures of these applications including the specifications, the drawings, and the claims are hereby incorporated by reference in its entirety.
BACKGROUNDThe technology disclosed in the present disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, the technology disclosed in the present disclosure relates to a transistor having a structure capable of inhibiting a reduction in the threshold voltage of a parasitic transistor formed in the vicinity of the edge of a shallow trench isolation (STI) and a method for fabricating the same.
As design rules for semiconductor devices have decreased, the degrees of integration of circuits have exponentially improved. For example, even a hundred of millions or more of field effect transistors (hereinafter referred to as FETs) can be mounted on a single chip. To achieve high integration of transistors, not only a reduction in gate length, but also a reduction in gate width is required. In the 45 nm generation using leading-edge semiconductor processes, miniaturized transistors having gate lengths of about 40 nm and gate widths of about 100 nm have been implemented. As a result, in the structure of transistors having narrow gate widths, the influence of a parasitic transistor has become non-negligible.
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Here,
As shown in
The parasitic transistors thus formed are assumed to be present in parasitic transistor formation regions A in the vicinities of the edges of a STI defining element formation regions in each of which a FET including a source region S, a drain region D, and a gate electrode G (having a gate length L and a gate width W) is formed, as shown in a plan view of
As described above, in the structure of a transistor having a narrow gate width, the influence of a parasitic transistor has become unignorable. This is because, due to factors such as an electric field concentration effect (the concentration of an electric field to an upper corner portion of a silicon substrate due to a gate bias) and the effect of a substrate impurity reduction (a reduction in the concentration of an impurity implanted in the silicon substrate for the adjustment of a threshold voltage, which results from the absorption of the impurity in an insulating film in a trench caused by a thermal process needed during the activation of a well and during the formation of a gate insulating film), the threshold voltage of each of the parasitic transistors formed in the parasitic transistor formation regions A tends to be lower than the threshold voltage of a transistor at the center portion of a gate electrode, as shown by the Id-Vg (drain current versus gate voltage) characteristic curve of
Since it is difficult to equalize the influence of the parasitic transistor given to the entire transistor including the transistor at the center portion, the Id-Vg characteristic of the entire transistor shown in
To prevent this, as shown in
In view of the foregoing, an object of the present disclosure is to provide a semiconductor device having a structure capable of inhibiting a reduction in the threshold voltage of a parasitic transistor, and a method for fabricating the same.
To attain the object, illustrative means according to the present disclosure will be shown below.
A semiconductor device includes: a first MIS transistor formed in a first element formation region of a semiconductor substrate; an isolation region formed in a trench provided in the semiconductor substrate to define the first element formation region; a first high-dielectric-constant gate insulating film formed over the first element formation region and the isolation region; and a first gate electrode formed on the first high-dielectric-constant gate insulating film, wherein a first portion of the first high-dielectric-constant gate insulating film formed between a portion of the first gate electrode located in the trench and a side surface of the first element formation region contains a first metal, and a second portion of the first high-dielectric-constant gate insulating film formed between the first gate electrode and an upper surface of the first element formation region does not contain the first metal.
In the semiconductor device described above, a lowermost surface of a region of the first gate electrode formed on the first portion of the first high-dielectric-constant gate insulating film is preferably at a position lower than a position of the upper surface of the first element formation region.
In the semiconductor device described above, at least a portion of the second portion of the first high-dielectric-constant gate insulating film spaced apart from the trench preferably does not contain the first metal.
In the semiconductor device described above, the isolation region may have: an isolation insulating film formed in the trench; a first underlying insulating film formed between the first element formation region and the isolation insulating film and at a sidewall portion of the trench; and a first protective film formed between the isolation insulating film and the first underlying insulating film, and containing the first metal.
In the semiconductor device described above, the first gate electrode may be formed on the side surface of the first element formation region with the first underlying insulating film, the first protective film, and the first portion of the first high-dielectric-constant gate insulating film interposed therebetween.
In the semiconductor device described above, the first underlying insulating film may be made of a silicon dioxide film or a silicon oxynitride film.
In the semiconductor device described above, when the first MIS transistor is an N-channel MIS transistor, the first protective film may be made of an aluminum film or an aluminum oxide film.
In the semiconductor device described above, when the first MIS transistor is an N-channel MIS transistor, the first metal may be aluminum.
In the semiconductor device described above, when the first MIS transistor is an N-channel MIS transistor, the second portion of the first high-dielectric-constant gate insulating film may contain any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium.
In the semiconductor device described above, when the first MIS transistor is a P-channel MIS transistor, the first protective film may be made of a film made of any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium or an oxide film of any one selected therefrom.
In the semiconductor device described above, when the first MIS transistor is a P-channel MIS transistor, the first metal may be lanthanum, dysprosium, scandium, erbium, or strontium.
In the semiconductor device described above, when the first MIS transistor is a P-channel MIS transistor, the second portion of the first high-dielectric-constant gate insulating film may contain aluminum.
In the semiconductor device described above, the first high-dielectric-constant gate insulating film may be made of a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxynitride film, a zirconium dioxide film, or a hafnium-zirconium oxide film.
In the semiconductor device described above, the first gate electrode has a film of at least one of titanium nitride, tantalum nitride, tantalum carbide, and tantalum carbonitride.
There may be a case where, in the semiconductor device described above, the isolation region defines the first element formation region, and a second element formation region of the semiconductor substrate where a second MIS transistor is formed, the semiconductor device further including: a second high-dielectric-constant gate insulating film formed over the second element formation region and the isolation region; and a second gate electrode formed on the second high-dielectric-constant gate insulating film, wherein a first portion of the second high-dielectric-constant gate insulating film formed between a portion of the second gate electrode located in the trench and a side surface of the second element formation region contains a second metal different from the first metal, and a second portion of the second high-dielectric-constant gate insulating film formed between the second gate electrode and an upper surface of the second element formation region does not contain the second metal.
In this case, the isolation region may have: an isolation insulating film formed in the trench; a first underlying insulating film formed between the first element formation region and the isolation insulating film and at a sidewall portion of the trench; a first protective film formed between the isolation insulating film and the first underlying insulating film, and containing the first metal; a second underlying insulating film formed between the second element formation region and the isolation insulating film and at a sidewall portion of the trench; and a second protective film formed between the isolation insulating film and the second underlying insulating film, and containing the second metal.
Further, when the first MIS transistor is an N-channel MIS transistor, and the second MIS transistor is a P-channel MIS transistor, the first protective film may be made of an aluminum film or an aluminum oxide film, and the second protective film may be made of a film made of any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium or an oxide film of any one selected therefrom.
Further, when the first MIS transistor is an N-channel MIS transistor, and the second MIS transistor is a P-channel MIS transistor, the first metal may be aluminum, and the second metal may be lanthanum, dysprosium, scandium, erbium, or strontium.
A method for fabricating a semiconductor device including a first MIS transistor formed in a first element formation region of a semiconductor substrate includes the steps of: (a) forming a trench defining the first element formation region in the semiconductor substrate, and then forming an isolation region in the trench; (b) forming a first high-dielectric-constant gate insulating film over the first element formation region and the isolation region; (c) forming a first gate electrode on the first high-dielectric-constant gate insulating film; and (d) introducing a first metal into a first portion of the first high-dielectric-constant gate insulating film formed between a portion of the first gate electrode located in the trench and a side surface of the first element formation region, wherein, in the step (d), the first metal is not introduced into a second portion of the first-high-dielectric-constant gate insulating film formed between the first gate electrode and an upper surface of the first element formation region.
In the method for fabricating the semiconductor device described above, the step (a) has the steps of: (a1) forming the trench in the semiconductor substrate; (a2) successively forming a first underlying insulating film and a first protective film containing the first metal at a sidewall portion of the trench in the first element formation region; and, (a3) after the step (a2), forming an isolation insulating film to fill the inside of the trench therewith, wherein the step (d) may include the step of introducing the first metal contained in the first protective film into the first high-dielectric-constant gate insulating film.
With the semiconductor device and the method for fabricating the same each described above, it is possible to inhibit a reduction in the threshold voltage of a parasitic transistor, and consequently reduce variations in transistors.
The following illustrative example embodiments are for clearly describing the technical idea of the present disclosure using drawings and a detailed description. Any person skilled in the art of the technical field concerned who has understood the preferred illustrative example embodiments of the present disclosure can modify or make an addition to the preferred illustrative example embodiments based on the technique disclosed in the present disclosure, and this would not depart from the technical idea and scope of the present disclosure.
First Illustrative Example EmbodimentA semiconductor device and a method for fabricating the same according to a first illustrative example embodiment of the present disclosure will be described. Specifically, a semiconductor device and a method for fabricating the same will be described below which can mitigate, in a structure (see
First, as shown in
Then, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Here, the description has been given to the case where the gate insulating film 110 is a HfO2 film, and the gate electrode 111 is a TiN film. However, the gate insulating film 110 and the gate electrode 111 are not limited to these thicknesses and materials. For example, as the gate insulating film 110, there may also be used a high-dielectric-constant material such as the hafnium oxide (HfO2) film mentioned above, a hafnium silicon oxide (HfSiO) film, a hafnium silicon oxynitride (HfSiON) film, a zirconium dioxide (ZrO2) film, or a hafnium-zirconium oxide (HfZrO) film. As the gate electrode 111, there may also be used a single-layer film of any one of the titanium nitride (TiN) film mentioned above, a tantalum nitride (TaN) film, a tantalum carbide (TaC) film, a tantalum carbonitride (TaCN) film, and the like, a laminated film of any two or more thereof, or a laminated film of any one thereof and a polysilicon film formed thereon. Further, by introducing lanthanum (La), dysprosium (Dy), scandium (Sc), erbium (Er), or strontium (Sr) into the portion of the gate insulating film 110 located over the substrate 100, it is possible to inhibit an increase in the threshold voltage of each of the NFETs in the upper portion of the substrate 100 due to the gate insulating film 110 made of the high-dielectric-constant material mentioned above.
As shown in
In the structure of the semiconductor device and the method for fabricating the same according to the first illustrative example embodiment described above, the structure is shown in which the protective film 106 is interposed between the underlying insulating film 105 and the aluminum-containing gate insulating films 110a in the vicinities of the edges of the STI region. However, the boundary of the protective film 106 need not be distinct. For example, even in a structure in which the underlying insulating film 105 and the aluminum-containing gate insulating films 110a are in contact with each other with an interface layer having a high aluminum concentration interposed therebetween, the same effects as described above are obtainable.
In the case of the structure of the semiconductor device and the method for fabricating the same according to the first illustrative example embodiment described above, the structure in which the NFETs are formed in the element formation regions defined by the STI region has been described as an example. However, even from a structure in which PFETs are formed instead of the NFETs, the same effects are obtainable. That is, as the protective film 106, a film containing a metal capable of increasing the threshold voltage of each of the parasitic transistors in the PFETs, and having an etching rate lower than that of the isolation insulating film may be used appropriately. For example, a film made of any one of lanthanum (La), dysprosium (Dy), scandium (Sc), erbium (Er), or strontium (Sr) or an oxide film of any one thereof is used. In this manner, it is possible to form a gate insulating film containing a metal capable of increasing the threshold voltage of each of the parasitic transistors in the PFETs, and therefore inhibit a reduction in the threshold voltage of the parasitic transistor. Also in this case, by introducing Al into the portion of the gate insulating film 110 located over the substrate 100, a threshold voltage increase due to the gate insulating film 110 made of the foregoing high-dielectric-constant material can be inhibited in the upper portion of the substrate 100. Note that, in the case of the structure in which PFETs are formed, an impurity implanted into the substrate 100 is an N-type impurity such as, e.g., arsenic or phosphorus.
In the case of forming the gate insulating film 110 by a CVD process, the gate insulating film 110 tends to be thinner in the divots 109 in the three-dimensional structure due to a reduced deposition speed. This causes concern about a reduction in the threshold voltage of the parasitic transistor due to the thinner gate insulating film 110. However, in the structure of the semiconductor device and the method for fabricating the same according to the first illustrative example embodiment described above, the protective film 106 is provided, and therefore a reduction in the threshold voltage of each of the parasitic transistors can be inhibited.
Second Illustrative Example EmbodimentA semiconductor device and a method for fabricating the same according to a second illustrative example embodiment of the present disclosure will be described. Specifically, a description will be given below to a semiconductor device and a method for fabricating the same which can inhibit, in a structure (see
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Here, the description has been given to the case where the gate insulating film 216 is a HfO2 film, and the gate electrode 217 is a TiN film. However, the gate insulating film 216 and the gate electrode 217 are not limited to these thicknesses and materials. For example, as the gate insulating film 216, there may also be used a high-dielectric-constant material such as a hafnium oxide (HfO2) film, a hafnium silicon oxide (HfSiO) film, a hafnium silicon oxynitride (HfSiON) film, a zirconium dioxide (ZrO2) film, or a hafnium-zirconium oxide (HfZrO) film. As the gate electrode 217, there may also be used a single-layer film of any one of the titanium nitride (TiN) film mentioned above, a tantalum nitride (TaN) film, a tantalum carbide (TaC) film, a tantalum carbonitride (TaCN) film, and the like, a laminated film of any two or more thereof, or a laminated film of any one thereof and a polysilicon film formed thereon. Further, by introducing lanthanum (La), dysprosium (Dy), scandium (Sc), erbium (Er), or strontium (Sr) into the portion of the gate insulating film 216 located over the substrate 200 in the NFET formation region, it is possible to inhibit an increase in the threshold voltage of the NFET in the upper portion of the substrate 200 due to the gate insulating film 216 made of the high-dielectric-constant material mentioned above. Likewise, by introducing Al into the portion of the gate insulating film 216 located over the substrate 200 in the PFET formation region, it is possible to inhibit an increase in the threshold voltage of the PFET in the upper portion of the substrate 200 due to the gate insulating film 216 made of the high-dielectric-constant material mentioned above.
As shown in
Since the aluminum-containing gate insulating film 216a is thus formed due to the presence of the protective film 206 in the vicinity of the edge of the STI region in the NFET formation region, even when the divot 215 is formed in the vicinity of the edge portion of the STI region, and a parasitic transistor is formed in the NFET, it is possible to inhibit a reduction in the threshold voltage of the parasitic transistor. Likewise, since the lanthanum-containing gate insulating film 216b is formed due to the presence of the protective film 208 in the vicinity of the edge of the STI region in the PFET formation region, even when the divot 215 is formed in the vicinity of the edge portion of the STI region, and a parasitic transistor is formed in the PFET, it is possible to inhibit a reduction in the threshold voltage of the parasitic transistor. In the case of the structure of the semiconductor device according to the second illustrative example embodiment, by providing the protective films 206 and 208, the threshold voltage of each of the parasitic transistors in the parasitic transistor formation regions 5A and 5B can be improved by about 200 mV. This allows a reduction in the characteristic variations of each of the transistors. In addition, as described above, the thickness of the underlying insulating film 205 may fall appropriately within a range of about 0.5 to 15 nm, and the thicknesses of the protective films 206 and 208 may fall appropriately within a range of about 0.5 to 2 nm. Therefore, even when the miniaturization of the transistors advances, the structure according to the second illustrative example embodiment is applicable thereto.
In the structure of the semiconductor device and the method for fabricating the same according to the second illustrative example embodiment described above, the structure is shown in which the protective film 206 is interposed between the underlying insulating film 205 and the aluminum-containing gate insulating film 216a or the protective film 208 is interposed between the underlying insulating film 205 and the lanthanum-containing gate insulating film 216b in the vicinity of the edge of the STI region. However, the boundaries of the protective films 206 and 208 need not be distinct. For example, even in a structure in which the underlying insulating film 205 and the aluminum-containing gate insulating film 216a are in contact with each other with an interface layer having a high aluminum concentration interposed therebetween or the underlying insulating film 205 and the lanthanum-containing gate insulating film 216b are in contact with each other with an interface layer having a high lanthanum concentration interposed therebetween, the same effects as described above are obtainable.
In the method for fabricating the semiconductor device according to the second illustrative example embodiment described above, the description has been given to the case where the protective film 206 made of, e.g., an aluminum oxide film is formed in the NFET formation region (see
In the case of forming the gate insulating film 216 by a CVD process, the gate insulating film 216 tends to be thinner in the divots 215 in the three-dimensional structure due to a reduced deposition speed. This causes concern about a reduction in the threshold voltage of the parasitic transistor due to the thinner gate insulating film 216. However, in the structure of the semiconductor device and the method for fabricating the same according to the second illustrative example embodiment described above, the protective films 206 and 208 are provided, and therefore a reduction in the threshold voltage of each of the parasitic transistors can be inhibited.
The present disclosure is useful for, e.g., a transistor having a high-dielectric-constant gate insulating film.
Claims
1. A semiconductor device, comprising:
- a first MIS transistor formed in a first element formation region of a semiconductor substrate;
- an isolation region formed in a trench provided in the semiconductor substrate to define the first element formation region;
- a first high-dielectric-constant gate insulating film formed over the first element formation region and the isolation region; and
- a first gate electrode formed on the first high-dielectric-constant gate insulating film, wherein
- a first portion of the first high-dielectric-constant gate insulating film formed between a portion of the first gate electrode located in the trench and a side surface of the first element formation region contains a first metal, and
- a second portion of the first high-dielectric-constant gate insulating film formed between the first gate electrode and an upper surface of the first element formation region does not contain the first metal.
2. The semiconductor device of claim 1, wherein a lowermost surface of a region of the first gate electrode formed on the first portion of the first high-dielectric-constant gate insulating film is at a position lower than a position of the upper surface of the first element formation region.
3. The semiconductor device of claim 1, wherein at least a portion of the second portion of the first high-dielectric-constant gate insulating film spaced apart from the trench does not contain the first metal.
4. The semiconductor device of claim 1, wherein the isolation region has:
- an isolation insulating film formed in the trench;
- a first underlying insulating film formed between the first element formation region and the isolation insulating film and at a sidewall portion of the trench; and
- a first protective film formed between the isolation insulating film and the first underlying insulating film, and containing the first metal.
5. The semiconductor device of claim 4, wherein the first gate electrode is formed on the side surface of the first element formation region with the first underlying insulating film, the first protective film, and the first portion of the first high-dielectric-constant gate insulating film interposed therebetween.
6. The semiconductor device of claim 4, wherein the first underlying insulating film is made of a silicon dioxide film or a silicon oxynitride film.
7. The semiconductor device of claim 4, wherein
- the first MIS transistor is an N-channel MIS transistor, and
- the first protective film is made of an aluminum film or an aluminum oxide film.
8. The semiconductor device of claim 1, wherein
- the first MIS transistor is an N-channel MIS transistor, and
- the first metal is aluminum.
9. The semiconductor device of claim 1, wherein
- the first MIS transistor is an N-channel MIS transistor, and
- the second portion of the first high-dielectric-constant gate insulating film contains any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium.
10. The semiconductor device of claim 4, wherein
- the first MIS transistor is a P-channel MIS transistor, and
- the first protective film is made of a film made of any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium or an oxide film of any one selected therefrom.
11. The semiconductor device of claim 1, wherein
- the first MIS transistor is a P-channel MIS transistor, and
- the first metal is lanthanum, dysprosium, scandium, erbium, or strontium.
12. The semiconductor device of claim 1, wherein
- the first MIS transistor is a P-channel MIS transistor, and
- the second portion of the first high-dielectric-constant gate insulating film contains aluminum.
13. The semiconductor device of claim 1, wherein
- the first high-dielectric-constant gate insulating film is made of a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxynitride film, a zirconium dioxide film, or a hafnium-zirconium oxide film.
14. The semiconductor device of claim 1, wherein
- the first gate electrode has a film of at least one of titanium nitride, tantalum nitride, tantalum carbide, and tantalum carbonitride.
15. The semiconductor device of claim 1, wherein
- the isolation region defines the first element formation region, and a second element formation region of the semiconductor substrate where a second MIS transistor is formed,
- the semiconductor device further comprising:
- a second high-dielectric-constant gate insulating film formed over the second element formation region and the isolation region; and
- a second gate electrode formed on the second high-dielectric-constant gate insulating film, wherein
- a first portion of the second high-dielectric-constant gate insulating film formed between a portion of the second gate electrode located in the trench and a side surface of the second element formation region contains a second metal different from the first metal, and a second portion of the second high-dielectric-constant gate insulating film formed between the second gate electrode and an upper surface of the second element formation region does not contain the second metal.
16. The semiconductor device of claim 15, wherein the isolation region has:
- an isolation insulating film formed in the trench;
- a first underlying insulating film formed between the first element formation region and the isolation insulating film and at a sidewall portion of the trench;
- a first protective film formed between the isolation insulating film and the first underlying insulating film, and containing the first metal;
- a second underlying insulating film formed between the second element formation region and the isolation insulating film and at a sidewall portion of the trench; and
- a second protective film formed between the isolation insulating film and the second underlying insulating film, and containing the second metal.
17. The semiconductor device of claim 16, wherein
- the first MIS transistor is an N-channel MIS transistor,
- the second MIS transistor is a P-channel MIS transistor,
- the first protective film is made of an aluminum film or an aluminum oxide film, and
- the second protective film is made of a film made of any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium or an oxide film of any one selected therefrom.
18. The semiconductor device of claim 15, wherein
- the first MIS transistor is an N-channel MIS transistor,
- the second MIS transistor is a P-channel MIS transistor,
- the first metal is aluminum, and
- the second metal is lanthanum, dysprosium, scandium, erbium, or strontium.
19. A method for fabricating a semiconductor device comprising a first MIS transistor formed in a first element formation region of a semiconductor substrate, the method comprising the steps of:
- (a) forming a trench defining the first element formation region in the semiconductor substrate, and then forming an isolation region in the trench;
- (b) forming a first high-dielectric-constant gate insulating film over the first element formation region and the isolation region;
- (c) forming a first gate electrode on the first high-dielectric-constant gate insulating film; and
- (d) introducing a first metal into a first portion of the first high-dielectric-constant gate insulating film formed between a portion of the first gate electrode located in the trench and a side surface of the first element formation region, wherein,
- in the step (d), the first metal is not introduced into a second portion of the first-high-dielectric-constant gate insulating film formed between the first gate electrode and an upper surface of the first element formation region.
20. The method of claim 19, wherein the step (a) has the steps of:
- (a1) forming the trench in the semiconductor substrate;
- (a2) successively forming a first underlying insulating film and a first protective film containing the first metal at a sidewall portion of the trench in the first element formation region; and,
- (a3) after the step (a2), forming an isolation insulating film to fill the inside of the trench therewith, wherein
- the step (d) includes the step of introducing the first metal contained in the first protective film into the first high-dielectric-constant gate insulating film.
Type: Application
Filed: Jun 3, 2010
Publication Date: Sep 23, 2010
Applicant: PANASONIC CORPORATION (Osaka)
Inventors: Shinji TAKEOKA (Toyama), Takashi NAKABAYASHI (Osaka)
Application Number: 12/793,613
International Classification: H01L 27/092 (20060101); H01L 21/762 (20060101);