Patents by Inventor Shogo Mochizuki

Shogo Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Differing device characteristics on a single wafer by selective etch
    Patent number: 10679901
    Abstract: Integrated chips and methods of forming the same include etching a first stack of layers in a first region and etching a second stack of layers in a second region. The first stack of layers includes a first semiconductor layer having a first thickness over a first sacrificial layer having a second thickness. Etching the first stack of layers removes the first sacrificial layer from the first stack of layers and creates a first gap. The second stack of layers includes a second semiconductor layer having a third thickness over a second sacrificial layer having a fourth thickness. Etching the second stack of layers removes the second sacrificial layer from the second stack of layers and to create a second gap. A dielectric material fills the first gap and the second gap.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Shogo Mochizuki, Gen Tsutsui, Ruqiang Bao
  • Channel Strain Formation in Vertical Transport FETS with Dummy Stressor Materials
    Publication number: 20200176333
    Abstract: Techniques for forming VTFET devices with tensile- and compressively-strained channels using dummy stressor materials are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source and drains at a base of the fins; forming bottom spacers on the bottom source and drains; growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins; surrounding the fins with a rigid fill material; removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the fins by the rigid fill material; forming replacement gate stacks in the gate trenches; forming top spacers on the replacement gate stacks; and forming top source and drains over the top spacers at tops of the fins. A VTFET device is also provided.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Choonghyun Lee, Kangguo Cheng, Shogo Mochizuki, Juntao Li
  • VERTICAL TRANSISTOR AND METHOD OF FORMING THE VERTICAL TRANSISTOR
    Publication number: 20200167331
    Abstract: A semiconductor device includes a source/drain (S/D) region, a fin structure formed on the S/D region, and a gate structure formed on the fin structure so that a space is formed between the S/D region and the gate structure.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Inventors: Fee Li LIE, Shogo MOCHIZUKI, Junli WANG
  • Vertical transistors with various gate lengths
    Patent number: 10665714
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, ChoongHyun Lee, Shogo Mochizuki
  • Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface
    Patent number: 10665698
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. The method includes forming a channel region comprising a channel region semiconductor material having a first energy band gap characteristic. A source region is formed communicatively coupled to the channel region. A drain region is formed communicatively coupled to the channel region. A gate region is formed communicatively coupled to the channel region. An enhanced band gap region is positioned substantially positioned at an interface between the channel region and the drain region. The enhanced band gap region includes an enhanced band gap region semiconductor material having a second band gap energy characteristic. The first energy band gap is less than the second energy band gap.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • SELF-ALIGNED BOTTOM SOURCE/DRAIN EPITAXIAL GROWTH IN VERTICAL FIELD EFFECT TRANSISTORS
    Publication number: 20200161451
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Choonghyun LEE, Ruqiang BAO, SHOGO MOCHIZUKI, Brent A. ANDERSON, Hemanth JAGANNATHAN
  • VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN JUNCTIONS
    Publication number: 20200161454
    Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee, Shogo Mochizuki
  • VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN JUNCTIONS
    Publication number: 20200161453
    Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee, Shogo Mochizuki
  • VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR STRUCTURE WITH SELF-ALIGNED TOP JUNCTION THROUGH EARLY TOP SOURCE/DRAIN EPITAXY
    Publication number: 20200152791
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • Forming a fin using double trench epitaxy
    Patent number: 10651295
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Low thermal budget top source and drain region formation for vertical transistors
    Patent number: 10651089
    Abstract: A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki, Oleg Gluschenkov
  • Self aligned top extension formation for vertical transistors
    Patent number: 10651308
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • VERTICAL TRANSPORT FET HAVING MULTIPLE THRESHOLD VOLTAGES WITH ZERO-THICKNESS VARIATION OF WORK FUNCTION METAL
    Publication number: 20200144378
    Abstract: A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 7, 2020
    Inventors: CHOONGHYUN LEE, KANGGUO CHENG, JUNTAO LI, SHOGO MOCHIZUKI
  • Forming Bottom Source and Drain Extension on Vertical Transport FET (VTFET)
    Publication number: 20200144419
    Abstract: Techniques for forming bottom source and drain extensions in VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming a liner at a base of the fins having a higher diffusivity for dopants than the fins; forming sidewall spacers alongside an upper portion of the fins; forming bottom source/drains on the liner at the base of the fins including the dopants; annealing the wafer to diffuse the dopants from the bottom source/drains, through the liner, into the base of the fins to form bottom extensions; removing the sidewall spacers; forming bottom spacers on the bottom source/drains; forming gate stacks alongside the fins above the bottom spacers; forming top spacers above the gate stacks; and forming top source/drains above the top spacers at tops of the fins. A VTFET device is also provided.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Inventors: Shogo Mochizuki, Kangguo Cheng, Juntao Li, Choonghyun Lee
  • Fin field-effect transistors with enhanced strain and reduced parasitic capacitance
    Patent number: 10644138
    Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, ChoongHyun Lee, Shogo Mochizuki
  • Surface area and Schottky barrier height engineering for contact trench epitaxy
    Patent number: 10643893
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 5, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita
  • Surface area and Schottky barrier height engineering for contact trench epitaxy
    Patent number: 10643894
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 5, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • MASKLESS TOP SOURCE/DRAIN EPITAXIAL GROWTH ON VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR
    Publication number: 20200135585
    Abstract: A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO2 layer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: ChoongHyun Lee, Shogo Mochizuki, Injo Ok, Soon-Cheon Seo
  • METHOD OF FORMING A TOP EPITAXY SOURCE/DRAIN STRUCTURE FOR A VERTICAL TRANSISTOR
    Publication number: 20200135920
    Abstract: A metal is formed into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin. A patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer is formed on the metal and a topmost surface of the ILD material. A metal induced layer exchange anneal is then employed in which the metal and doped semiconductor material change places such that the doped semiconductor material is in direct contact with the topmost surface of the semiconductor fin. The exchanged doped semiconductor material, which provides a top source/drain structure of the vertical transistor, may have a different crystalline orientation than the topmost surface of the semiconductor fin.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: Dexin Kong, Kangguo Cheng, Shogo Mochizuki
  • REDUCING GATE-INDUCED-DRAIN-LEAKAGE CURRENT IN A TRANSISTOR BY FORMING AN ENHANCED BAND GAP LAYER AT THE CHANNEL-TO-DRAIN INTERFACE
    Publication number: 20200127122
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. The method includes forming a channel region comprising a channel region semiconductor material having a first energy band gap characteristic. A source region is formed communicatively coupled to the channel region. A drain region is formed communicatively coupled to the channel region. A gate region is formed communicatively coupled to the channel region. An enhanced band gap region is positioned substantially positioned at an interface between the channel region and the drain region. The enhanced band gap region includes an enhanced band gap region semiconductor material having a second band gap energy characteristic. The first energy band gap is less than the second energy band gap.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki