Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220171543
    Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.
    Type: Application
    Filed: November 17, 2021
    Publication date: June 2, 2022
    Inventors: Kim Soon Jway, Shu-Lin Lai, Yi-Ping Kuo
  • Patent number: 11344010
    Abstract: A dip net provided with a lockable and foldable handle comprises a handle, a hoop and a hoop mounting base, wherein the hoop mounting base is fixed to the front end of the handle and comprises a base body, a rotary shaft and a lock device; and the rotary shaft and the lock device are both mounted in the base body; connecting pieces are arranged at two ends of the rear side of the hoop and are respectively connected with two ends of the rotary shaft; the rotary shaft is provided with two clamping grooves in a circumferential direction; when the handle is unfolded, the lock device is matched with one clamping groove to realize locking; and when the handle is folded, the lock device is matched with the other clamping groove to realize locking. The dip net of the invention is more convenient to use and capable of saving time and labor.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 31, 2022
    Assignee: HANGZHOU FUFAN INDUSTRY CO., LTD.
    Inventors: Hongjian Xu, Shu Lin, Linrong Hong, Huihai Ge, Xiong Li
  • Patent number: 11342850
    Abstract: The present disclosure provides a forward converter with secondary LCD connected in parallel to realize forward and backward energy transmission, comprising a forward converter main circuit and an energy transfer and transmission circuit. The forward converter main circuit includes a high-frequency transformer T, a switching tube S, a diode D1, a diode D2, an inductance L1, and a capacitor C1. The energy transfer and transmission circuit includes a diode D3, a capacitor C2 and an inductance L2.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 24, 2022
    Assignee: XI'AN MORDA CORE ELECTRONICS TECHNOLOGY CO., LTD
    Inventors: Shu Lin Liu, Bo Yang, Jun Yang
  • Publication number: 20220149030
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20220141144
    Abstract: Stateful inspection and classification of packets is disclosed. A first differentiated services header value (DSHV) to associate with a first packet type and a corresponding first quality of service treatment is received from a configuration interface for a first packet type associated with a network traffic flow originating from a first application type. A second DSHV is received from the configuration interface to associate with a second packet type. A first packet having the first packet type is received and the first quality of service treatment is applied to the first packet. A second packet having the second packet type is received and the second quality of service treatment is applied to the second packet.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Philip Kwan, Shu Lin
  • Publication number: 20220141184
    Abstract: Techniques for providing flow meta data exchanges between network and security functions for a security service are disclosed. In some embodiments, a system/process/computer program product for providing flow meta data exchanges between network and security functions for a security service includes receiving a flow at a network gateway of a security service from a software-defined wide area network (SD-WAN) device; inspecting the flow to determine meta information associated with the flow; and communicating the meta information associated with the flow to the SD-WAN device.
    Type: Application
    Filed: July 14, 2021
    Publication date: May 5, 2022
    Inventors: Anand Oswal, Arivu Mani Ramasamy, Bhaskar Bhupalam, Shu Lin
  • Patent number: 11323037
    Abstract: The present disclosure provides a forward converter with secondary LCD connected in series to realize excitation energy transfer, comprising a forward converter main circuit and an energy transfer and transmission circuit. The forward converter main circuit includes a high-frequency transformer T, a switching tube S, a diode D1, a diode D2, an inductance L1, and a capacitor C1. The energy transfer and transmission circuit includes a diode D3, a capacitor C2, and an inductance L2. The circuit structure of the present disclosure has simple circuit structure and high reliability. And the reverse recovery problem of the diode could be eliminated by the soft switch-off or soft switch-on of the switching tube, which further reducing the loss of switching tube and diodes and improving the overall efficiency. In addition, the excitation energy could be transferred to the load side to improve the energy transmission efficiency.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 3, 2022
    Assignee: XI'AN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Shu Lin Liu, Yi Jun Shen, Xue Ting Li, Yin Qiao Peng, Ji Zhi Yan
  • Patent number: 11302600
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Chien-Yuan Huang, Chen-Hsiang Lao
  • Publication number: 20220102288
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Hsuan-Ning Shih, Hsien-Pin Hu, Tsung-Shu Lin, Tsung-Yu Chen, Wen-Hsin Wei
  • Patent number: 11289398
    Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°<?<90°. The heat spreader is disposed over the substrate, wherein the semiconductor device is disposed between the heat spreader and the substrate. The adhesive layer is surrounding the semiconductor device and attaching the heat spreader onto the substrate, wherein the adhesive layer has a first opening misaligned with one of corners of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Publication number: 20220093526
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11282825
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Patent number: 11276656
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • Patent number: 11271900
    Abstract: Described herein are systems, methods, and software to enhance failover operations in a cloud computing environment. In one implementation, a method of operating a first service instance in a cloud computing environment includes obtaining a communication from a computing asset, wherein the communication comprises a first destination address. The method further provides replacing the first destination address with a second destination address in the communication, wherein the second destination address comprises a shared address for failover from a second service instance. After replacing the address, the method determines whether the communication is permitted based on the second destination address, and if permitted, processes the communication in accordance with a service executing on the service instance.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 8, 2022
    Assignee: Palo Alto Networks, Inc.
    Inventors: Shu Lin, Patrick Xu, Eswar Rao Sadaram, Hao Long
  • Publication number: 20220069127
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.
    Type: Application
    Filed: September 27, 2020
    Publication date: March 3, 2022
    Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
  • Patent number: 11258715
    Abstract: Stateful inspection and classification of packets is disclosed. For a first packet associated with a network traffic flow, a differentiated services header value (DSHV) is determined to associate with the first packet. The DSHV is used to perform a lookup of a quality of service treatment associated with the DSHV. The treatment is applied to the first packet. A determination is made, for a second packet associated with the network traffic flow, to associate a second DSHV with the second, where the second DSHV is different from the first DSHV.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 22, 2022
    Assignee: Palo Alto Networks, Inc.
    Inventors: Philip Kwan, Shu Lin
  • Publication number: 20220041588
    Abstract: Provided are certain RET inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: September 26, 2019
    Publication date: February 10, 2022
    Inventors: Chengxi HE, Rui TAN, Zuwen ZHOU, Weipeng ZHANG, Yunling WANG, Qihong LIU, Xingdong ZHAO, Yanxin LIU, Yuwei GAO, Shu LIN, Weibo WANG
  • Publication number: 20220045987
    Abstract: Techniques for providing localization at scale for a cloud-based security service are disclosed. In some embodiments, a system/method/computer program product for providing localization at scale for a cloud-based security service includes receiving a connection request at a network gateway of a cloud-based security service; performing a source Network Address Translation (NAT) from a registered set of public IP addresses associated with a tenant; and providing secure access to a Software as a Service (SaaS) using the cloud-based security service.
    Type: Application
    Filed: December 11, 2020
    Publication date: February 10, 2022
    Inventors: Thomas Arthur Warburton, Shu Lin, Devendra Raut, Jialiang Li, Hao Long
  • Patent number: 11226352
    Abstract: An electrical connection assembly includes a main body and a spring. One end of the main body is configured to be in contact with a device under test. The spring is sleeved around the main body. Two ends of the spring are respectively defined as a first end and a second end. The first end is abutted against a limiting protrusion, and a concealed section of the main body is correspondingly arranged inside of the spring. The spring has a first tightly-coiled section, an elastic section, and a second tightly-coiled section in sequence from the first end to the second end. A pitch of the spring within the elastic section is greater than a pitch of the spring within the first tightly-coiled section, and the pitch of the spring within the elastic section is greater than a pitch of the spring within the second tightly-coiled section.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 18, 2022
    Assignee: C.C.P.CONTACT PROBES CO., LTD.
    Inventors: Shu-Lin Wu, Yen-Wei Lin, Wei-Chu Chen, Bor-Chen Tsai
  • Publication number: 20220013407
    Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsin Chan, Jiing-Feng Yang, Kuan-Wei Huang, Meng-Shu Lin, Yu-Yu Chen, Chia-Wei Wu, Chang-Wen Chen, Wei-Hao Lin, Ching-Yu Chang