Abstract: According to one embodiment, a semiconductor memory device includes a first array extending in a first direction, a second array extending in the first direction, and a second electrode film. The second array is arranged with the first array in a second direction crossing the first direction. The second electrode film provided between the first array and the second array. The second electrode film extends in the first direction. Each of the first array and the second array include a first structure, a second structure arranged in the first direction, a fourth insulating film provided between the first structure and the second structure, and a third insulating film provided between the first structure and the second electrode film, provided also between the first structure and the fourth insulating film.

Abstract: An object of the present invention is to provide methods of discovering drugs effective for tough targets, which have conventionally been discovered only with difficulty. The present invention relates to novel methods for cyclizing peptide compounds, and novel peptide compounds and libraries comprising the same, to achieve the above object.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Abstract: A pneumatic tire comprising: first carcass ply that is comprised of; a tire-inner-face part extending along inner face of the tire to span between the tire bead portions; and turned-up parts extended as turned up from outer faces of the tire bead portions up to inside beyond fringes of a belt layer; and second carcass ply that is substantially omitted at between the tire bead portions and extends as being turned up from outer faces of the tire bead portions up to inside beyond fringes of a belt layer; and cords forming the tire-inner-face part, the turned-up part and the second carcass ply having inclination to radial direction of the tire; and direction of the inclination of the cords being alternated in respect of leftward or rightward, between two adjacent ones of the tire-inner-face part, the turned-up part and the second carcass ply.

Abstract: According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage.

Abstract: A pneumatic tire comprising: first carcass ply that is comprised of; a tire-inner-face part extending along inner face of the tire to span between the tire bead portions; and turned-up parts extended as turned up from outer faces of the tire bead portions up to inside beyond fringes of a belt layer; and second carcass ply that is substantially omitted at between the tire bead portions and extends as being turned up from outer faces of the tire bead portions up to inside beyond fringes of a belt layer; and cords forming the tire-inner-face part, the turned-up part and the second carcass ply having inclination to radial direction of the tire; and direction of the inclination of the cords being alternated in respect of leftward or rightward, between two adjacent ones of the tire-inner-face part, the turned-up part and the second carcass ply.

Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.

Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor pillar, a first electrode film, a second electrode film, a first insulating film, a second insulating film, and a wiring film. The semiconductor member is extending in a first direction. The first electrode film is disposed at the lateral side of the semiconductor member away from the semiconductor member. The second electrode film is provided between the semiconductor member and the first electrode film. The first insulating film is provided between the semiconductor member and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode film. The wiring film is disposed in a wiring lead-out region adjacent to the memory cell region. And the first electrode film is formed of a material different from a material of the wiring film, and being electrically connected to the wiring film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a semiconductor pillar provided on the substrate to extend in a vertical direction, a plurality of first electrode films provided sideward of the semiconductor pillar to extend in a first direction. The plurality of first electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a plurality of second electrode films provided between the semiconductor pillar and the first electrode films. The plurality of second electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a first insulating film provided between the semiconductor pillar and the second electrode films, and a second insulating film provided between the second electrode film and the first electrode film.

Abstract: The present invention aims to ensure strength of a thin-walled sintered magnet. A sintered magnet is a ferrite sintered magnet made by sintering a magnetic material. A magnetic powder mixture obtained by mixing magnetic powder with a binder resin is injection-molded into a mold with a magnetic field applied thereto to produce a molded body, which is then sintered to produce the sintered magnet. The sintered magnet has a thickness of 3.5 mm or less in the position of center of gravity thereof. The sintered magnet has a surface roughness Rz of 0.1 ?m or more and 2.5 ?m or less. The surface roughness Rz is a 10 point average roughness.

Abstract: An object of the present invention is to provide methods of discovering drugs effective for tough targets, which have conventionally been discovered only with difficulty. The present invention relates to novel methods for cyclizing peptide compounds, and novel peptide compounds and libraries comprising the same, to achieve the above object.

Abstract: According to one embodiment, a non-volatile semiconductor memory device, includes: peripheral transistors including a second element isolation insulating film, a gate electrode, and a diffusion layer region, the second element isolation insulating film being configured to divide the semiconductor layer into at least two second semiconductor regions, the diffusion layer region being formed in the second semiconductor regions to be provided on two sides of the gate electrode; and a sidewall film provided at a side surface of the gate electrode. The second element isolation insulating film has a first portion and a second portion, the second portion is provided on two sides of the first portion, a width of a bottom portion of the first portion in an extension direction of the gate electrode is not more than twice a thickness of the sidewall film at a lower end of the sidewall film.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a cell transistor, an extraction section, a guard ring, a first transistor, and a second transistor. The semiconductor substrate includes first, second, third, and fourth regions. The fourth region includes first and second portions. The cell transistor is provided on the first region and includes a first insulating film, a charge storage film, and a first electrode. The extraction section is provided on the second region and includes a second insulating film, and an extension electrode. The guard ring is provided on the third region and includes a third insulating. The first transistor is provided on the first portion and includes a fourth insulating, and a second electrode. The second transistor is provided on the second portion and includes a fifth insulating film, and a third electrode.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a cell transistor, an extraction section, a guard ring, a first transistor, and a second transistor. The semiconductor substrate includes first, second, third, and fourth regions. The fourth region includes first and second portions. The cell transistor is provided on the first region and includes a first insulating film, a charge storage film, and a first electrode. The extraction section is provided on the second region and includes a second insulating film, and an extension electrode. The guard ring is provided on the third region and includes a third insulating. The first transistor is provided on the first portion and includes a fourth insulating, and a second electrode. The second transistor is provided on the second portion and includes a fifth insulating film, and a third electrode.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.

Abstract: According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film.

Abstract: A ceramic substrate has a base material composed of an amorphous phase and particles composed of a crystalline phase and dispersed in the base material. Some of the particles are permitted to protrude from at least one surface of the base material. The amorphous phase can contain glass and the crystalline phase can contain a crystalline filler.

Abstract: According to one embodiment, a semiconductor memory device has plural memory cells arranged on a semiconductor substrate, plural select transistors for selecting the memory cell for carrying out record or read, and an insulating film arranged between adjacent memory cells and between adjacent select transistors. The memory cell and select cell transistors include gates extending the same distance from the substrate, and an insulator between adjacent select cell transistors, between the select cell transistors and the memory transistors, and between adjacent memory transistors, the height of the insulator between the select cell transistors is higher than between the select cell transistors and the memory transistors, and between adjacent memory transistors. An insulating layer deposited thereover is deposited having an in situ flatness, without further planarization.

Abstract: A pneumatic tire comprising: first carcass ply that is comprised of; a tire-inner-face part extending along inner face of the tire to span between the tire bead portions; and turned-up parts extended as turned up from outer faces of the tire bead portions up to inside beyond fringes of a belt layer; and second carcass ply that is substantially omitted at between the tire bead portions and extends as being turned up from outer faces of the tire bead portions up to inside beyond fringes of a belt layer; and cords forming the tire-inner-face part, the turned-up part and the second carcass ply having inclination to radial direction of the tire; and direction of the inclination of the cords being alternated in respect of leftward or rightwards, between two adjacent ones of the tire-inner-face part, the turned-up part and the second carcass ply.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.