Patents by Inventor Tetsuya Itano

Tetsuya Itano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9661249
    Abstract: An image capturing apparatus includes: plural pixels arranged in matrix, each outputting a signal from a photoelectric conversion element; and plural readout circuits each provided for a corresponding column of the pixels, signals from the pixels being input to the readout circuits. The readout circuit includes an amplifier unit configured to amplify the signal from the pixel, and have a variable gain, and a hold capacitance connected to an output terminal of the amplifier unit via a sampling switch, and having a variable capacitance value. When the variable gain of the amplifier unit is set to be a first gain, the variable capacitance value of the hold capacitance is set to be a first capacitance value. When the variable gain is set to be a second gain larger than the first gain, the variable capacitance value is set to be a second capacitance value smaller than the first capacitance value.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: May 23, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohichi Nakamura, Tetsuya Itano, Hideo Kobayashi
  • Patent number: 9654716
    Abstract: The present invention relates to a technology for providing a selection unit configured to perform selection of a bit memory that holds a signal of a first bit of a digital signal from among a plurality of bit memories commonly in a memory unit in each of a plurality of AD conversion units.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 16, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hidetoshi Hayashi, Hiroki Hiyama, Tetsuya Itano, Toshiaki Ono, Tatsuhiko Yamazaki
  • Patent number: 9602752
    Abstract: A solid-state imaging apparatus includes: a pixels in a matrix for generating a pixel signal; and A/D converting units, corresponding to columns of the matrix, to convert the pixel signal into a n-bit digital value. The A/D converting units includes first storage units for storing the n-bit digital value one bit by one bit, and second storage units corresponding to the first storage units, to hold the digital value transferred from the first storage unit. In each of the columns of the plurality of pixels, arranged corresponding thereto are the first storage units and the second storage units form n-pairs. Each pair including the first storage unit and the second storage unit hold the digital value of the same bit. The n-pairs are arrayed in a matrix.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: March 21, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hideo Kobayashi, Kohichi Nakamura, Tetsuya Itano, Yasushi Matsuno
  • Publication number: 20160358968
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Publication number: 20160344968
    Abstract: A driving method for an image pickup apparatus includes accumulating a signal generated during a first charge accumulation period by a first sub pixel, accumulating a signal generated during a second charge accumulation period partially overlapped with the first charge accumulation period by a second sub pixel, and controlling column circuits such that, after processing of the signal generated during the first charge accumulation period is performed, processing of the signal is performed which is generated during the second charge accumulation period of the second sub pixel included in the pixel where the signal processing of the first sub pixel is performed, and the column circuits are put into a non-operating state during at least part of a period after the processing of the signal generated during the first charge accumulation period is ended until the second charge accumulation period is ended.
    Type: Application
    Filed: March 28, 2016
    Publication date: November 24, 2016
    Inventors: Kei Ochiai, Tetsuya Itano, Mineo Uchida
  • Publication number: 20160309101
    Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 20, 2016
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
  • Patent number: 9467636
    Abstract: A photoelectric conversion device includes a plurality of pixels arranged in a plurality of columns, a plurality of comparators provided correspondingly to the respective columns, a reference signal generation unit configured to supply a reference signal to the plurality of comparators, a counter configured to generate a count signal that includes a plurality of bits in synchronization with a first clock signal, a synchronization unit configured to synchronize the plurality of bits with a second clock signal to generate a synchronized count signal and to output the generated synchronized count signal, and a plurality of memories provided correspondingly to the respective comparators, the memories each being configured to store the synchronized count signal in response to a change in an output of a corresponding one of the comparators.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: October 11, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohichi Nakamura, Koichiro Iwata, Kazuhiro Saito, Takeshi Akiyama, Tetsuya Itano, Hiroki Hiyama, Takashi Muto
  • Patent number: 9450011
    Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: September 20, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
  • Patent number: 9443895
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 13, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Patent number: 9438841
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: September 6, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Patent number: 9438828
    Abstract: Provided is a photoelectric conversion apparatus including: a pixel array having pixels arranged in matrix; a pixel output line provided according to each column of the pixel array and transmitting a pixel signal output from a pixel of each column of the pixel array; a column signal processing unit provided according to each column of the pixel array and into which the pixel signal is input from the pixel output line, in which the column signal processing unit has a plurality of horizontal adding up or averaging units configured to add up or average the plurality of pixel signals based on the pixels of different columns of the pixel array; and a plurality of adding up or averaging modes with different numbers of columns subjected to adding up or averaging can be selected by selectively using one or a plurality of the plurality of horizontal adding up or averaging units.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: September 6, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kohichi Nakamura, Hideo Kobayashi
  • Publication number: 20160227141
    Abstract: A solid-state image sensor includes a pixel array having pixels, an AD converter configured to generate digital signals by AD-converting analog signals output from the pixel array, a plurality of memories, and an output line. A horizontal transfer period in which the plurality of memories sequentially output digital signals to the output line includes first and second periods. In the first period, digital signals having a predetermined value are continuously output to the output line from a plurality of first memories out of the plurality of memories. In the second period, the digital signals which have been AD-converted by the AD converter are output to the output line from a plurality of second memories, separate from the plurality of first memories, out of the plurality of memories.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 4, 2016
    Inventors: Hideo Kobayashi, Tetsuya Itano, Kohichi Nakamura
  • Patent number: 9385152
    Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Publication number: 20160156865
    Abstract: The present invention relates to a technology for providing a selection unit configured to perform selection of a bit memory that holds a signal of a first bit of a digital signal from among a plurality of bit memories commonly in a memory unit in each of a plurality of AD conversion units.
    Type: Application
    Filed: November 23, 2015
    Publication date: June 2, 2016
    Inventors: Hidetoshi Hayashi, Hiroki Hiyama, Tetsuya Itano, Toshiaki Ono, Tatsuhiko Yamazaki
  • Publication number: 20160156868
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 2, 2016
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Publication number: 20160156866
    Abstract: An image pickup apparatus includes a plurality of pixels arranged in rows and columns, a plurality of comparators, each of the comparators including a switch for controlling an operation, a signal line which is provided commonly to the switches of the plurality of comparators and through which a control signal for controlling the switches of the plurality of comparators is supplied, a control signal generation unit, and a signal line control unit configured to control an electric potential of the signal line to be set as a fixed electric potential.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 2, 2016
    Inventors: Kohichi Nakamura, Tetsuya Itano, Hiroki Hiyama, Hiroaki Kameyama, Kazuhiro Saito
  • Patent number: 9344652
    Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 17, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
  • Patent number: 9338377
    Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 10, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
  • Publication number: 20160126280
    Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Inventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
  • Patent number: 9307174
    Abstract: A solid-state imaging apparatus includes a plurality of pixels arrayed in a matrix, and configured to generate signals by photoelectric conversion; a plurality of read-out circuits disposed on each column of the plurality of pixels arrayed in a matrix pattern, and configured to read out the signals from the plurality of pixels; a plurality of comparison units configured to compare the signals output from the plurality of read-out circuits with a reference signal whose level changes with time; a counter configured to count a clock signal after the level of the reference signal starts a change; a storage unit configured, when a magnitude relationship between the signals output from the plurality of the read-out circuits and the reference signal is reversed; and a reset unit configured to reset the count value stored in the storage unit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Hiroki Hiyama, Kazuhiro Saito, Kohichi Nakamura, Yu Maehashi