Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT
    Publication number: 20080266932
    Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Thomas Happ, Jan Boris Philipp, Ming-Hsiu Lee
  • STACKED SONOS MEMORY
    Publication number: 20080258203
    Abstract: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
    Type: Application
    Filed: April 19, 2007
    Publication date: October 23, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Resistive memory including bipolar transistor access devices
    Patent number: 7436695
    Abstract: A memory includes a first bipolar transistor, a first bit line, and a first resistive memory element coupled between a collector of the first bipolar transistor and the first bit line. The memory includes a second bit line, a second resistive memory element coupled between an emitter of the first bipolar transistor and the second bit line, and a word line coupled to a base of the first bipolar transistor.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 14, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Nirschl, Thomas Happ, Klaus Aufinger
  • OPTIMIZED PHASE CHANGE WRITE METHOD
    Publication number: 20080232158
    Abstract: A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Inventors: Mark Lamorey, Thomas Happ
  • Sense circuit for resistive memory
    Patent number: 7426134
    Abstract: A memory includes a phase-change memory cell and a circuit. The phase-change memory cell can be set to at least three different states including a substantially crystalline state, a substantially amorphous state, and at least one partially crystalline and partially amorphous state. The circuit applies a first voltage across the memory cell to determine whether the memory cell is set at the substantially crystalline state and applies a second voltage across the memory cell to determine whether the memory cell is set at a partially crystalline and partially amorphous state.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: September 16, 2008
    Assignee: Infineon Technologies North America
    Inventors: Thomas Happ, Matthew J. Breitwisch, Hsiang-Lang Lung
  • Phase change memory having multilayer thermal insulation
    Patent number: 7417245
    Abstract: A memory cell includes a first electrode, a second electrode, phase-change material contacting the first electrode and the second electrode, multilayer thermal insulation contacting the phase-change material, and dielectric material contacting the multilayer thermal insulation. The multilayer thermal insulation may include at least an electrically isolating layer and an electrically conducting layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 26, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Resistive memory including buried word lines
    Publication number: 20080185571
    Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 7, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Phase Change Memory Cell Design with Adjusted Seam Location
    Publication number: 20080179591
    Abstract: A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on the second surface region of the lower electrode and has one or more sidewalls. The spacer feature is also disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature. The dielectric layer is formed at least partially on top of the first surface region of the lower electrode and abutting the spacer feature.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Inventors: Matthew J. Breitwisch, Thomas Happ, Alejandro Gabriel Schrott
  • Integrated circuit to identify read disturb condition in memory cell
    Patent number: 7405964
    Abstract: A method of operating a phase change memory array is disclosed and includes identifying a read disturb condition associated with the phase change memory array, and performing a conditional refresh operation in response to the identified read disturb condition. A phase change memory is also disclosed and includes an array of phase change memory cells, and a read disturb system configured to identify a read disturb condition and perform a refresh operation on the array in response thereto.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: July 29, 2008
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Memory device electrode with a surface structure
    Patent number: 7405418
    Abstract: The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: July 29, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Cay-Uwe Pinnow, Michael Kund
  • Intergrated circuit for programming resistive memory cells
    Patent number: 7400528
    Abstract: Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: July 15, 2008
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Michael Kund
  • Resistance Limited Phase Change Memory Material
    Publication number: 20080165569
    Abstract: A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Inventors: Chieh-Fang Chen, Shih-Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
  • METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING A MEMORY INCLUDING A LOW-K DIELECTRIC MATERIAL
    Publication number: 20080158943
    Abstract: The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an isolation material. The phase-change material is coupled adjacent the first electrode. The second electrode is coupled adjacent the phase-change material. The isolation material adjacent the phase-change material thermally isolates the phase-change material.
    Type: Application
    Filed: March 18, 2008
    Publication date: July 3, 2008
    Inventors: Thomas Happ, Shoaib Zaidi
  • MEMORY HAVING STORAGE LOCATIONS WITHIN A COMMON VOLUME OF PHASE CHANGE MATERIAL
    Publication number: 20080158942
    Abstract: A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change material for accessing a second storage location within the volume of phase change material.
    Type: Application
    Filed: March 17, 2008
    Publication date: July 3, 2008
    Applicant: Infineon Technologies AG
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Phillipp
  • Pillar phase change memory cell
    Publication number: 20080149909
    Abstract: A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than the first cross-sectional width. The first electrode, the storage location, and the second electrode form a pillar phase change memory cell.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Inventors: Jan Boris Philipp, Thomas Happ
  • Phase change memory device with thermal insulating layers
    Patent number: 7391050
    Abstract: A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: June 24, 2008
    Assignee: Infineon Technologies AG
    Inventor: Thomas Happ
  • INTEGRATED CIRCUIT INCLUDING A MEMORY FABRICATED USING SELF-ALIGNED PROCESSING
    Publication number: 20080142778
    Abstract: An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
    Type: Application
    Filed: January 28, 2008
    Publication date: June 19, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • Optical determination of resistivity of phase change materials
    Patent number: 7388667
    Abstract: A system includes a non-contacting optical measurement instrument and a controller. The non-contacting optical measurement instrument is configured to obtain a measurement of a phase-change material. The controller is configured to determine a resistivity of the phase-change material based on the measurement.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: June 17, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Shoaib Hasan Zaidi
  • Memory cell with trigger element
    Publication number: 20080123398
    Abstract: A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Resistive memory including refresh operation
    Publication number: 20080117663
    Abstract: A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 22, 2008
    Inventors: Jan Boris Philipp, Thomas Happ