Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090052232
    Abstract: A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material.
    Type: Application
    Filed: July 3, 2008
    Publication date: February 26, 2009
    Applicant: QIMONDA AG
    Inventors: Dieter Andres, Thomas Happ, Petra Majewski, Bernhard Ruf
  • Patent number: 7495946
    Abstract: A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: February 24, 2009
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • Publication number: 20090046498
    Abstract: An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.
    Type: Application
    Filed: November 30, 2007
    Publication date: February 19, 2009
    Applicant: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Publication number: 20090045385
    Abstract: An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.
    Type: Application
    Filed: June 23, 2008
    Publication date: February 19, 2009
    Applicant: QIMONDA AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20090046499
    Abstract: An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.
    Type: Application
    Filed: February 5, 2008
    Publication date: February 19, 2009
    Applicant: QIMONDA AG
    Inventors: Jan Boris Philipp, Luca De Ambroggi, Peter Schroegmeier, Gernot Steinlesberger, Christian Pho Duc, Franz Kreupl, Thomas Happ
  • Publication number: 20090020738
    Abstract: An integrated circuit includes a first electrode, a second electrode, and force-filled resistivity changing material electrically coupled to the first electrode and the second electrode.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 22, 2009
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20090014704
    Abstract: A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 15, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
  • Patent number: 7474555
    Abstract: A phase change memory cell includes a MOS select transistor having a gate coupled to a word line, and a source and drain region coupled between first and second bit lines, respectively. A first phase change element is coupled between the first bit line and the source region of the MOS select transistor. A method of reading a selected cell in the array is provided by evaluating a body effect impact of a state of the phase change element associated with the selected cell on a MOS select transistor.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: January 6, 2009
    Inventors: Thomas Nirschl, Thomas Happ
  • Publication number: 20090001341
    Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
  • Publication number: 20090003046
    Abstract: One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.
    Type: Application
    Filed: May 15, 2008
    Publication date: January 1, 2009
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Publication number: 20090003035
    Abstract: One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 1, 2009
    Inventors: Jan Boris Philipp, Thomas Happ, Thomas Nirschl
  • Publication number: 20090003032
    Abstract: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Jan Boris Philipp, Thomas Happ
  • Publication number: 20090003044
    Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20090003034
    Abstract: One embodiment of the present invention relates to a method of programming an array of memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, each of which can write at least two data states to the memory cells of the array. Other embodiments are also disclosed.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20080315173
    Abstract: An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode and the second electrode.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Inventors: Jan Boris Philipp, Thomas Happ
  • Publication number: 20080316802
    Abstract: A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20080315359
    Abstract: An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20080316793
    Abstract: An integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Inventors: Jan Boris Philipp, Thomas Happ
  • Publication number: 20080315172
    Abstract: An integrated circuit includes a vertical diode defined by crossed line lithography.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20080316794
    Abstract: An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Inventors: Jan Boris Philipp, Thomas Happ