Abstract: A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on the second surface region of the lower electrode and has one or more sidewalls. The spacer feature is also disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature. The dielectric layer is formed at least partially on top of the first surface region of the lower electrode and abutting the spacer feature.

Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

Abstract: A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.

Abstract: A method for manufacturing at least one resistively switching memory cell including generating a first electrode; depositing a phase change material layer, the phase change material layer including a composition of formula GaxGeyInzSb1-x-y-z that also incorporates at least elemental oxygen or elemental nitrogen, where x, y, and z are each between 0 and 1 and the sum of x, y, and z is less than or equal to 1; and generating a second electrode, the phase change material layer in working relation with the first electrode and with the second electrode.

Abstract: An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element.

Abstract: A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material.

Abstract: A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.

Abstract: An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.

Abstract: An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.

Abstract: An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.

Abstract: An integrated circuit includes a first electrode, a second electrode, and force-filled resistivity changing material electrically coupled to the first electrode and the second electrode.

Abstract: A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

Abstract: A phase change memory cell includes a MOS select transistor having a gate coupled to a word line, and a source and drain region coupled between first and second bit lines, respectively. A first phase change element is coupled between the first bit line and the source region of the MOS select transistor. A method of reading a selected cell in the array is provided by evaluating a body effect impact of a state of the phase change element associated with the selected cell on a MOS select transistor.

Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.

Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element.

Abstract: One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.

Abstract: One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.

Abstract: One embodiment of the present invention relates to a method of programming an array of memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, each of which can write at least two data states to the memory cells of the array. Other embodiments are also disclosed.

Abstract: An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode and the second electrode.