Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistive memory including bipolar transistor access devices
    Publication number: 20080117667
    Abstract: A memory includes a first bipolar transistor, a first bit line, and a first resistive memory element coupled between a collector of the first bipolar transistor and the first bit line. The memory includes a second bit line, a second resistive memory element coupled between an emitter of the first bipolar transistor and the second bit line, and a word line coupled to a base of the first bipolar transistor.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventors: Thomas Nirschl, Thomas Happ, Klaus Aufinger
  • System that prevents reduction in data retention
    Publication number: 20080117697
    Abstract: One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the configuration data in the resistive memory.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 22, 2008
    Inventors: Jan Boris Philipp, Thomas Happ
  • Resistive memory including selective refresh operation
    Publication number: 20080117704
    Abstract: A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit having resistive memory
    Patent number: 7372725
    Abstract: A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured to provide pulses to the phase-change material and to program each of more than two states into the memory cell. The second circuit is configured to sense the present state of the memory cell and provide signals that indicate the present state of the memory cell. The first circuit programs each of the more than two states into the memory cell based on the signals.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: May 13, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • ENERGY ADJUSTED WRITE PULSES IN PHASE-CHANGE MEMORY CELLS
    Publication number: 20080106928
    Abstract: An integrated circuit that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least a first and a second state. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for at least some of the phase-change memory cells in accordance with the temperature sensed by the temperature sensor.
    Type: Application
    Filed: January 10, 2008
    Publication date: May 8, 2008
    Inventors: Thomas Happ, Zaidi Shoaib
  • Combined read/write circuit for memory
    Publication number: 20080101110
    Abstract: A memory device includes an array portion of resistive memory cells organized in rows and columns, wherein the rows correspond to word lines and the columns correspond to bit lines. The device further includes a combined read/write circuit associated with each respective bit line in the array portion configured to read from or write to a resistive memory cell associated with the respective bit line.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 1, 2008
    Inventors: Thomas Happ, Thomas Nirschl
  • Phase change memory fabricated using self-aligned processing
    Patent number: 7362608
    Abstract: A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines encapsulated by dielectric material in rows across the array. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory includes phase change elements between the second conductive lines and contacting the first conductive lines and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: April 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • Integrated circuit having a memory including a low-k dielectric material for thermal isolation
    Patent number: 7361925
    Abstract: The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an isolation material. The phase-change material is coupled adjacent the first electrode. The second electrode is coupled adjacent the phase-change material. The isolation material adjacent the phase-change material thermally isolates the phase-change material.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: April 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Shoaib Zaidi
  • Semiconductor device including multi-bit memory cells and a temperature budget sensor
    Publication number: 20080084738
    Abstract: One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is programmable into each of more than two states. The circuit compares a first signal from the first temperature budget sensor to a first reference signal to obtain a first comparison result. The circuit refreshes the plurality of multi-bit memory cells based on the first comparison result.
    Type: Application
    Filed: October 6, 2006
    Publication date: April 10, 2008
    Inventors: Jan Boris Philipp, Thomas Happ
  • Resistive memory having shunted memory cells
    Publication number: 20080080228
    Abstract: A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current divider with a selected memory cell during a read operation.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 3, 2008
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Phase change memory cell with high read margin at low power operation
    Patent number: 7348590
    Abstract: A memory cell device includes a first electrode, a heater adjacent the first electrode, phase-change material adjacent the heater, a second electrode adjacent the phase-change material, and isolation material adjacent the phase-change material for thermally isolating the phase-change material.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: March 25, 2008
    Assignee: Infineon Technologies AG
    Inventor: Thomas Happ
  • Resistive memory having shunted memory cells
    Publication number: 20080068878
    Abstract: A memory includes a bit line, a plurality of resistive memory cells coupled to the bit line, and a resistor. The resistor is coupled to the bit line to form a current divider with a selected memory cell during a read operation.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 20, 2008
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Memory having storage locations within a common volume of phase change material
    Patent number: 7345899
    Abstract: A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change material for accessing a second storage location within the volume of phase change material.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: March 18, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Phase change memory array having equalized resistance
    Patent number: 7339814
    Abstract: A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first line plus the second line at each one of the memory cells is substantially equal.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: March 4, 2008
    Assignee: Infineon Technologies AG
    Inventor: Thomas Happ
  • Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size
    Patent number: 7332377
    Abstract: The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned etching of the word lines that constitute simultaneously the top electrodes of the memory cells, and of the CB memory cells themselves. An advantage of the inventive method consists in that no via lithography is required, so that the manufacturing method is easier to perform, less expensive, and yields reliable results.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: February 19, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Ralf Symanczyk
  • Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state
    Patent number: 7329561
    Abstract: A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: February 12, 2008
    Assignee: Infineon Technologies, AG
    Inventors: Ralf Symanczyk, Cay-Uwe Pinnow, Thomas Happ
  • Energy adjusted write pulses in phase-change memories
    Patent number: 7327623
    Abstract: A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least two states. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for the plurality of phase-change memory cells with the temperature sensed by the temperature sensor.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: February 5, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Zaidi Shoaib
  • Read disturb sensor for phase change memories
    Publication number: 20080025079
    Abstract: A method of operating a phase change memory array is disclosed and includes identifying a read disturb condition associated with the phase change memory array, and performing a conditional refresh operation in response to the identified read disturb condition. A phase change memory is also disclosed and includes an array of phase change memory cells, and a read disturb system configured to identify a read disturb condition and perform a refresh operation on the array in response thereto.
    Type: Application
    Filed: July 27, 2006
    Publication date: January 31, 2008
    Inventors: Jan Boris Philipp, Thomas Happ
  • Phase change memory fabricated using self-aligned processing
    Patent number: 7324365
    Abstract: A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: January 29, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • INTEGRATED CIRCUIT HAVING MEMORY HAVING A STEP-LIKE PROGRAMMING CHARACTERISTIC
    Publication number: 20080019170
    Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material has a step-like programming characteristic.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 24, 2008
    Inventors: Thomas Happ, Jan Boris Philipp