Abstract: Provided are an electrode plate and a secondary battery having the same. The electrode plate comprises a current collector and an active material layer, wherein the current collector comprises a main body portion and tabs, the active material layer is coated on the surface of the main body portion, and the tabs extend from one end of the main body portion along the first direction; a first insulating portion is formed on the end face of the main body portion that is provided with the tabs, and a second insulating portion different from the first insulating portion is formed on the end faces of the main body portion that are not provided with the tabs. The electrode plate of the present application has a good end-face insulation protection and can improve the safety performance of the secondary battery.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.

Abstract: The present application discloses a composition, an adhesive film including the composition and a chip packaging structure. The composition includes epoxy resin, a surfactant, a curing agent and filler, wherein the surfactant is selected from a modified hexafluoropropylene compound. The surfactant in the composition is the modified hexafluoropropylene compound, the modified hexafluoropropylene compound is lower in surface energy, good in water resistance and oil resistance and capable of effectively lowering the surface tension of the composition, and therefore, when being used for preparing the adhesive film, the composition is higher in coating wettability. In addition, the composition has stronger chemical cleaning resistance, and in a process that a residual solder flux obtained in a soldering process of a chip is cleaned, a chip protection film prepared from the composition has stronger cleaning resistance to an alkaline solution so as not to be easy to fall off.

Abstract: A multi-signal fluorescent probe, represented by: A method for preparing the multi-signal fluorescent probe includes: (a) adding 2-methoxyphenothiazine and ethyl iodide into a mixture of dichloromethane (DCM) and acetonitrile followed by a first reaction and a first post-treatment to obtain 10-ethyl-2-methoxy-10H-phenothiazine; (b) adding boron tribromide into the 10-ethyl-2-methoxy-10H-phenothiazine under an inert gas followed by a second reaction under an ice bath and a second post-treatment to obtain 10-ethyl-10H-phenothiazin-2-ol; and (c) mixing the 10-ethyl-10H-phenothiazin-2-ol, malonic acid, zinc chloride and phosphorus oxychloride followed by a third reaction and a third post-treatment to obtain the multi-signal fluorescent probe. A use of the multi-signal fluorescent probe in the detection of intracellular ONOO? and Na2S2 is also provided.

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

Abstract: Disclosed is a preservation method for fresh wet rice noodles or fresh wet brown rice noodles, belonging to the technical field of food. According to the present disclosure, ?-polylysine hydrochloride, pyrophosphate, glycerol, sodium chloride, a highly water-soluble starch-dextrin complex, rice flour and water are mixed together, and the obtained mixture is stirred evenly to obtain a mixed system; and extrusion forming, first-stage aging, re-steaming, second-stage aging and rehydration are performed on the mixed system to obtain the fresh wet rice noodles or fresh wet brown rice noodles. Furthermore, the present disclosure employs a combination of thermodynamic sterilization and chemical preservation to preserve the fresh wet rice noodles, thereby prolonging the shelf life of the fresh wet rice noodles or fresh wet brown rice noodles to 2 months or more and keeping the quality thereof good.

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

Abstract: A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

Abstract: A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.

Abstract: The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of one of the particles with a ray-tracing method by a parallel processing thread in a hardware accelerator, identifying a surface normal of a voxel unit in the voxel mesh that intersects the flight path by the parallel processing thread, determining a surface reaction between the one of the particles and the voxel unit by a central processing unit (CPU), and updating the voxel mesh based on the determining of the surface reaction.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of at least one of the particles with a ray-tracing method, identifying a voxel unit in the voxel mesh that intersects the flight path, determining a surface reaction between the one of the particles and the voxel unit, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the surface reaction.

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Abstract: A rigid-flexible coupling-driven robot for removing oxide scales on super large shaft forgings online includes a heavy-duty manipulator main body, four walking systems, a movable arm lifting system, a clamping system, a power system, two oxide scale removal systems and a visual identification system. The two oxide scale removal systems are respectively installed on the two trapezoidal plates of the clamping system. Each of the two oxide scale removal systems adopts rigid-flexible coupling drive technology, that is, the rigid drive of the overhead hydraulic cylinder, cable-stayed hydraulic cylinder, the long stroke scissor retractable bracket and the rack and pinion device is combined with the flexible drive of the wire rope, so that the retraction and the angle tilt of the parallelogram end removal device are realized, which makes the oxide scale removal more flexible and efficient, thus greatly improving the product quality of large forgings.

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.