Patents by Inventor Ting Li

Ting Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11558548
    Abstract: Systems and methods for encoding regions containing an element of interest in a sequence of images with a high resolution are provided. Such systems and methods can include a camera that can capture the sequence of images of a monitored region, a detection processor that can identify a first region that contains an element of interest within the sequence of images, and an encoder that can encode the first region within a first subset of the sequence of images with a first resolution and encode a second region within the first subset of the sequence of images outside of the first region with a second resolution that is less than the first resolution, wherein a number of the sequence of images in the first subset of the sequence of images is less than all of the sequence of images and is based on a predefined parameter.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: January 17, 2023
    Assignee: ADEMCO INC.
    Inventors: Ting Li, Xiaoxiang Lin, Jun Wu
  • Patent number: 11557508
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-Li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Publication number: 20230011163
    Abstract: The invention discloses the application of a ?-N-acetylhexosaminidase (HaHex74) from Haloferula sp. in the synthesis of human milk oligosaccharides. The invention provides the use of HaHex74 protein or related biological materials thereof in any one of the following: synthesizing human milk oligosaccharides; synthesizing Lacto-N-triose II and/or Lacto-N-neotetraose; the HaHex74 protein having the amino acid sequence shown in SEQ ID No. 2 is derived from Haloferula sp. The ?-N-acetylhexosaminidase HaHex74 disclosed by the invention possesses high-level expression, excellent hydrolysis properties and transglycosylation activity, which may make it potentially useful in the production of human milk oligosaccharides.
    Type: Application
    Filed: October 20, 2020
    Publication date: January 12, 2023
    Inventors: Zhengqiang JIANG, Yihao LIU, Shaoqing YANG, Junwen MA, Qiaojuan YAN, Ting LI
  • Publication number: 20220413181
    Abstract: Methods, systems, and computer programs are presented for determining flood levels within a region. One method includes an operation for detecting an alert generated by one of a riverine, a coastal, or an urban model. Further, the method includes operations for selecting one or more regions for estimating flood data based on the detected alert, and for calculating, by an inundation model, region flood data for each of the selected regions based on outputs from the riverine model, the coastal model, and the urban model. Additionally, the method includes an operation for combining the region flood data for the selected one or more regions to obtain combined flood data. The combined flood data is presented on a user interface, such as on a flood inundation map.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Ahmad Wani, Nicole Hu, Feyera Hirpa, Wang Zhan, Shabaz Patel, Samuel Lamont, Yi Liu, Zhuo Liu, Ting Li, Yu Zhang
  • Publication number: 20220413106
    Abstract: A pulsed light source illuminates a scene with a virtual array of points. Light reflected by the scene is detected by a small pixel array, allowing generation of a three-dimensional map of the scene. A processing element processing data output by the small pixel array uses a multipath resolution algorithm to resolve individual objects in the scene.
    Type: Application
    Filed: August 28, 2022
    Publication date: December 29, 2022
    Inventors: Baher HAROUN, Rahmi HEZAR, Srinath RAMASWAMY, Nirmal C. WARKE, David MAGEE, Ting LI
  • Publication number: 20220378858
    Abstract: The present invention relates to compositions comprising one or more compounds and/or extracts which induce, promote and/or improve production/release/delivery/excretion of mucin from and/or in the cornea, and methods of using the compositions to treat the eye.
    Type: Application
    Filed: May 5, 2022
    Publication date: December 1, 2022
    Inventors: Wen-Hwa Ting Li, Khalid Mahmood, Ramine Parsa, Manpreet Randhawa, Mingqi Bai, Kenneth T. Holeva
  • Publication number: 20220367347
    Abstract: A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li YANG, Po-Hao TSAI, Ching-Wen HSIAO, Hong-Seng SHUE, Yu-Tse SU
  • Patent number: 11489296
    Abstract: A power supply includes a cover body, a metal plate, a metal clip, a circuit board and a housing. The metal plate is partially disposed in a first space of the cover body. The metal clip is disposed in the first space and electrically connected to the metal plate, and includes an upper spring piece, a lower spring piece and a connecting piece. The connecting piece has a fixing portion corresponding to a gap between the upper and lower spring pieces. The circuit board includes an input portion and an output portion. The input portion is disposed in the gap, and has a protruding part for engaging with the fixing portion. The housing includes an output interface and an opening communicating with an accommodating space of the housing. The cover body is connected to the opening. The output interface is electrically connected to the output portion.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 1, 2022
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Hsieh-Ting Li, Yen-Chih Chen, Po-Sheng Lee
  • Patent number: 11484031
    Abstract: A seed coating agent for preventing and treating a wheat rot disease is provided. The seed coating agent includes a fungicide and a seed priming and elicitor. The fungicide includes silthiopham and coumoxystrobin. The seed priming and elicitor includes salicylic acid and compound sodium nitrophenolate. The weight percentage of each components is 1%-60% of the fungicide, 0.0005%-0.05% of salicylic acid, and 0.001%-0.1% of compound sodium nitrophenolate. The seed coating agent has a good effect of promoting seed germination and strengthening seedlings on wheat seeds. Both silthiopham and coumoxystrobin are of low toxicity, and are safe for humans, animals, beneficial organisms, and the environment.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: November 1, 2022
    Inventors: Wei Zhao, Rende Qi, Yuankai Chi, Shun Cao, Xiaofang Cui, Ting Li, Tao Wang
  • Publication number: 20220331746
    Abstract: Disclosed are a light-driven filtration antibacterial composite membrane and a preparation method and use thereof. The method for preparing the light-driven filtration antibacterial composite membrane includes: mixing dichloromethane and N,N-dimethylformamide to obtain a first solution; adding PCL particles to the first solution, and stirring until being uniform to obtain an electrospinning solution; adding a ZIF-8 powder to the electrospinning solution, and ultrasonically dispersing for at least 1 hour to obtain a PCL/ZIF-8 spinning solution; spraying the PCL/ZIF-8 spinning solution onto a PPCL@PDA/TAEG men-blown membrane to obtain the light-driven filtration antibacterial composite membrane.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 20, 2022
    Applicants: Tiangong University, Minjiang University, Tianjin Yuzhan International Trade Co., Ltd.
    Inventors: Ting-Ting LI, Lu Yang, Heng Zhang, Bo Gao, Jia-Horng Lin, Ching-Wen Lou
  • Publication number: 20220321136
    Abstract: A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.
    Type: Application
    Filed: July 26, 2019
    Publication date: October 6, 2022
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Ting LI, Gangyi HU, Ruzhang LI, Yong ZHANG, Dongbing FU, Zhengbo HUANG, Yabo NI, Jian'an WANG, Guangbing CHEN
  • Patent number: 11460551
    Abstract: A pulsed light source illuminates a scene with a virtual array of points. Light reflected by the scene is detected by a small pixel array, allowing generation of a three-dimensional map of the scene. A processing element processing data output by the small pixel array uses a multipath resolution algorithm to resolve individual objects in the scene.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher Haroun, Rahmi Hezar, Srinath Ramaswamy, Nirmal C. Warke, David Magee, Ting Li
  • Publication number: 20220308407
    Abstract: The present application discloses a display panel and a display device, which include a plurality of sub-pixels, and each of sub-pixel includes a first pixel electrode with a first pixel voltage and a second pixel electrode with a second pixel voltage; when the sub-pixels are in a low-gray-scale state, the second pixel voltage and the first pixel voltage have a first ratio; when the sub-pixels are in a high-gray-scale state, the second pixel voltage and the first pixel voltage have a second ratio, and the second ratio is greater than the first ratio.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 29, 2022
    Inventors: Yoonsung UM, Jing LIU, Kaili QU, Chuwei LIANG, Ziqi LIU, Ting LI, Lintao LIU
  • Patent number: 11456047
    Abstract: Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: September 27, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Huangpeng Zhang, Shiyang Yang, Yu Wang, Huamin Cao, Ting Li, Xu Hou
  • Publication number: 20220288841
    Abstract: A production line for producing components to a high standard of cleanliness and sealed and protected in that state includes a loading device, a cleaning device, a detecting device, a pasting device, a heat-sealing device, a packing device, and transfer devices of the production line. The production line automatically processes the components for obtaining components with the high cleanliness. By the processes of protective film pasting, heat-sealing, and packing, the components may be further protected from subsequent pollution. A method for producing components with a high cleanliness applied to the production line is also disclosed.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 15, 2022
    Inventors: JIAN-WEN GAO, TING-TING LI, CHU-HUI WU, AI-JUN TANG, HUI WANG, SHI CHEN, BO YANG, FENG ZHANG, KUN-LIANG LIN, JIAN-GANG ZHANG
  • Publication number: 20220274827
    Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 1, 2022
    Inventors: Ting-Li YANG, Kai-Di WU, Ming-Da CHENG, Wen-Hsiung LU, Cheng Jen LIN, Chin Wei KANG
  • Publication number: 20220271208
    Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 25, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Jeng-Ting Li, Chi-Hai Kuo, Cheng-Ta Ko, Pu-Ju Lin
  • Patent number: 11423948
    Abstract: The present disclosure provides a storage chassis and an electronic device including the storage chassis. The storage chassis has a first receiving space at an upper portion of a rear end, the first receiving space is configured to be shared by a plurality of functional modules, and each functional module includes cable management supports, CPU computation control modules or storage hard disks. In the present disclosure, more modules can be arranged in a limited chassis space flexibly and reasonably, thereby improving the utilization of the chassis space and implementing configuration of various functions.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 23, 2022
    Inventors: Wenjin Li, Yu Wang, Shanping Huang, Ting Li
  • Patent number: 11416717
    Abstract: A classification model building apparatus and a classification model building method thereof are provided. The classification model building apparatus introduces a clustering algorithm to assist in training a deep learning model for classification and takes a sum of a clustering loss function, a center concentration loss function and a classification loss function multiplied by different weights, respectively, as a total loss function for training the deep learning model. Based on the total loss function, the classification model building apparatus adjusts parameters of the deep learning model through a backpropagation algorithm to build a classification model.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 16, 2022
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Chen-Kuo Chiang, Hao-Ting Li, Chih-Cheng Lin
  • Publication number: 20220246565
    Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.
    Type: Application
    Filed: October 1, 2021
    Publication date: August 4, 2022
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Ming-Da Cheng