Patents by Inventor TING YEH

TING YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296864
    Abstract: A power device and a method for visualizing information thereof are provided. The power device is configured to provide operation power to at least one load. The power device comprises a display interface and a control circuit. The control circuit is configured to display a color icon by the display interface, so as to show at least one of a system status and a system setting of the power device by the color icon.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 23, 2021
    Applicant: CYBER POWER SYSTEMS, INC.
    Inventors: LIEN-HSUN HO, SHOU-TING YEH, YI-PING TSAO, TSAI-JUNG CHAN, CHENG-YEN LO
  • Publication number: 20210296734
    Abstract: The disclosure provides a separator comprising a porous substrate and a heat-resistant layer disposed on a surface of the substrate. The heat-resistant layer comprises a binder and a plurality of inorganic particles, wherein the heat-resistant layer is disposed on the surface of the porous substrate in the range of 10% to 90% of the total surface area of the porous substrate.
    Type: Application
    Filed: January 28, 2021
    Publication date: September 23, 2021
    Inventors: WEI-TING YEH, YI-FANG HUANG, KAI-WEI CHENG, YU-RUEI LI, WAN-TING LO
  • Publication number: 20210296498
    Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Wei-Yang Lee, Tzu-Hsiang Hsu, Ting-Yeh Chen, Feng-Cheng Yang
  • Publication number: 20210288044
    Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Chih-Ting YEH, Che-Hao CHUANG
  • Publication number: 20210286234
    Abstract: Examples of shutter assembly are described herein. In an example, the shutter assembly includes an opening having a magnetic rubber-based shutter disposed in the opening. The magnetic rubber-based shutter is slidable along a length of the opening to selectively cover and expose the camera.
    Type: Application
    Filed: December 15, 2017
    Publication date: September 16, 2021
    Inventors: Ya-Ting Yeh, Kuan-Ting Wu, Shih-Hsun Huang
  • Publication number: 20210288003
    Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.
    Type: Application
    Filed: November 10, 2020
    Publication date: September 16, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ying-Lin CHEN, Ting-Yeh WU
  • Publication number: 20210273114
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.
    Type: Application
    Filed: December 18, 2020
    Publication date: September 2, 2021
    Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20210273101
    Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang LEE, Ting-Yeh CHEN, Chii-Horng LI, Feng-Cheng YANG
  • Patent number: 11107734
    Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Ting-Yeh Chen
  • Publication number: 20210217632
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Application
    Filed: November 10, 2020
    Publication date: July 15, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ting-Yeh WU
  • Publication number: 20210216744
    Abstract: An electronic device and a manufacturing method for the electronic device are provided. The electronic device includes a display structure layer and a light sensing panel. The light sensing panel includes a first substrate; a second substrate, wherein the second substrate is disposed between the first substrate and the display structure layer; a plurality of sensing units, disposed on the first substrate and between the first substrate and the second substrate; and an optical structure layer, disposed on the second substrate and between the second substrate and the display structure layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: July 15, 2021
    Inventors: Yu-Tsung Liu, Hui-Ching Yang, Te-Yu Lee, Tao-Sheng Chang, Ting-Yeh Chi
  • Publication number: 20210217641
    Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.
    Type: Application
    Filed: August 20, 2020
    Publication date: July 15, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ying-Lin CHEN, Ting-Yeh WU
  • Patent number: 11056481
    Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 6, 2021
    Assignee: AMAZING MICROELECTRONIC CORP.
    Inventors: Chih-Ting Yeh, Che-Hao Chuang
  • Publication number: 20210202699
    Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20210194277
    Abstract: An off-line uninterruptible power system and two line-interactive uninterruptible power systems are provided. The off-line uninterruptible power system and one of the line-interactive uninterruptible power systems additionally adopt a transformer for supplying an AC output, with lower voltage level than a rated output voltage, to at least one electrical device (especially those with resistive load characteristic). The other line-interactive uninterruptible power system controls its automatic voltage regulating circuit to supply an AC output, with lower voltage level than a rated output voltage, to at least one electrical device (especially those with resistive load characteristic).
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: LIEN-HSUN HO, SHOU-TING YEH, JUI-HUNG CHOU, KAI-TSUNG YANG
  • Publication number: 20210175483
    Abstract: The present disclosure relates to a ceramic separator. The ceramic separator comprises a porous polyolefin substrate and a ceramic layer on the at least one surface of the porous polyolefin substrate. The ceramic layer comprises polydopamine-surface-decorated inorganic particles and a water-based binder. In addition to the necessary physical properties of common separators, the ceramic separator has excellent wettability and rate of absorption so as to improve the capacity and stability of batteries at a high battery discharge rate.
    Type: Application
    Filed: May 5, 2020
    Publication date: June 10, 2021
    Inventors: Kai-Wei CHENG, Mei-Sia LYU, Wei-Ting YEH
  • Patent number: 11031498
    Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Tzu-Hsiang Hsu, Ting-Yeh Chen, Feng-Cheng Yang
  • Publication number: 20210165193
    Abstract: A photographing optical lens assembly includes seven lens elements, the seven lens elements being, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements includes an object-side surface facing towards the object side and an image-side surface facing towards the image side. The image-side surface of the seventh lens element is concave in a paraxial region thereof and includes at least one inflection point in an off-axis region thereof.
    Type: Application
    Filed: February 3, 2021
    Publication date: June 3, 2021
    Inventors: Kuan-Ting YEH, Hsin-Hsuan HUANG
  • Publication number: 20210165465
    Abstract: In one example, a hinge assembly may include a first hinge member and a second hinge member. The first hinge member may include a first hinge base and a first hinge bracket pivotally connected to the first hinge base. The second hinge member may include a second hinge base and a second hinge bracket pivotally connected to the second hinge base. Further, the hinge assembly may include a hydraulic unit connected between the first hinge member and the second hinge member to provide synchronous movements between the first hinge bracket and the second hinge bracket.
    Type: Application
    Filed: June 6, 2018
    Publication date: June 3, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Shih-Hsun Huang, Ya-Ting Yeh
  • Patent number: 11022529
    Abstract: The invention provides enrichment platform devices for size-based capture of particles in solution. The enrichment platform device is useful for label-free capture of any particle. The invention relates to enrichment platform devices using nanowires and vertically aligned carbon nanotubes. The invention provides methods for making the enrichment platform devices. The invention provides methods for using the enrichment platform devices for filtering particles, capturing particles, concentrating particles, and releasing viable particles.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: June 1, 2021
    Assignee: The Penn State Research Foundation
    Inventors: Siyang Zheng, Mauricio Terrones, Yin-Ting Yeh, Yi Tang, Huaguang Lu, Nestor Perea Lopez, Yiqiu Xia