Abstract: A defect inspection system is disclosed, and comprises a linear light source, N number of cameras, a display device, a tag reader, and a modular electronic device, in which the linear light source, the cameras and the modular electronic device are used for conducting a defect inspection of an article. On the other hand, the display device, the tag reader and the modular electronic device are adopted for conducting in production of at least one labeled example. Therefore, the modular electronic device is allowed to apply a machine learning process to an image classifier under using a training dataset containing the labeled examples, thereby producing at least one new defect recognition model or updating the existing defect recognition model.

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Abstract: The disclosure provides a method for manufacturing a separator, comprising the steps of: providing a nonporous precursor substrate; coating a heat-resistant slurry on a surface of the nonporous precursor substrate to form a heat-resistant coating layer, wherein the heat-resistant slurry comprises a binder and a plurality of inorganic particles; and stretching the nonporous precursor substrate with the heat-resistant coating layer formed thereon to generate a separator comprising a porous substrate and a heat-resistant layer; wherein the heat-resistant layer is disposed on the surface of the porous substrate in the range of 10% to 90% of the total surface area of the porous substrate.

Abstract: A motor controlling system is disclosed. The motor controlling system is integrated in an apparatus having roll-to-roll mechanism, and comprises a linear light source, N number of cameras and a modular electronic device. When a roll of continuous web material is discharged by an unwinding unit of the roll-to-roll mechanism so as to be further transferred to an inspection unit, the cameras are controlled by the modular electronic device to capture a plurality of time-consecutive material image frames. Subsequently, the modular electronic device conducts a defection inspection for a segment of the continuous web material by applying an image process to the material image frames. As a result, in case of there being at least one defect found, the modular electronic device stops a plurality of motors of the apparatus from running, thereby making the segment of the continuous web material be positioned on an inspection platform.

Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

Abstract: The disclosure provides a separator comprising a porous substrate and a heat-resistant layer disposed on a surface of the substrate. The heat-resistant layer comprises a binder and a plurality of inorganic particles, wherein the heat-resistant layer is disposed on the surface of the porous substrate in the range of 10% to 90% of the total surface area of the porous substrate.

Abstract: This application describes covers for electronic devices, electronic devices, and methods for making the covers. In one example, a cover comprises a substrate comprising a first metal; a second metal injection molded 10 on the surface of the substrate; a paint layer or an electrophoretic deposition layer on the second metal surface; a chamfered edge on the substrate, wherein the chamfered edge cuts through the paint layer or the electrophoretic deposition layer, the second metal, and partially through the first metal; and a hydrophobic coating.

Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.

Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

Abstract: A near-field communication (NFC) antenna structure for radiation enhancement of a computing device that includes a ferrite sheet, separated into two sections. The NFC antenna structure may be used to improve (i) the magnetic field strength generated by an NFC antenna and (ii) inductive coupling to a receiving antenna of another computing device. A first ferrite section may be placed on a first side of the NFC antenna to at least partially overlap the NFC antenna, and a second ferrite section may be placed on a second side (opposite the first side) to at least partially overlap the NFC antenna. The first ferrite section may be positioned towards a top end that is often positioned closest to a receiving device, as held by a user when performing a contactless communication of the computing device, to increase the magnetic field strength and improve the inductive coupling at the top end.

Abstract: The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.

Abstract: An optical imaging system includes six lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has negative refractive power, and the object-side surface of the first lens element is concave in a paraxial region thereof. The image-side surface of the second lens element is concave in a paraxial region thereof. The fourth lens element has negative refractive power. The image-side surface of the sixth lens element is concave in a paraxial region thereof and has at least one critical point in an off-axis region thereof.

Abstract: Embodiments relate to a bioagent capture and identification system including a microfluidic platform for label-free, size-based capture, enrichment, and optical profiling of bioagents using vertically aligned carbon nanotubes coated in gold nanoparticles. Bioagent identification can be automated using machine learning. Captured bioagents remain viable after capture and analysis. In the nanotube fabrication process, catalyst precursor layers are fabricated using patterned stamps. In addition, nanotube diameter and density are increased by increasing the concentration of metal content in the catalyst precursor layer.