Patents by Inventor TING YEH

TING YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230320589
    Abstract: A sole data collection device and a sole data collection method are disclosed. The sole data collection device includes an image capture module, a temperature detection module and a monofilament testing module. The sole data collection device is used for collecting the sole data of a user, and the sole data is transmitted to a cloud server. The sole data collection device and the sole data collection method are not only convenient for a user to collect sole data at home at any time, but also allow the user's caregiver and/or relevant medical care personnel to extract the sole data from the cloud server to screen the user's plantar condition, so as to solve the problem that it is time-consuming and costly to go to a medical institution for relevant examinations.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 12, 2023
    Inventors: TING-TING YEH, MIAO-YU LIAO, CHIA-CHIH CHANG, YU-SYUAN CHEN, I-FENG HSU
  • Publication number: 20230319083
    Abstract: Techniques for performing point-in-time relative outlier detection are disclosed herein. In some embodiments, an outlier detection system analyzes metric data based on (a) the values of the metric data detected on a computing resource, (b) a relative change between different metric readings and/or (c) an absolute change between different metric readings relative to the point in time. The outlier detection system may predict whether the computing resource is exhibiting anomalous behavior by applying a set of machine-learning (ML) models to the point-in-time values. The ML models allow the outlook detection system to make inferences and adjustments during application runtime rather than relying on static instruction sets to detect and classify outliers. The ML models that are applied may implement unsupervised learning methods that do not rely on pre-training and/or time-series analysis for classification.
    Type: Application
    Filed: December 9, 2022
    Publication date: October 5, 2023
    Applicant: Oracle International Corporation
    Inventors: Diego Ceferino Torres Dho, Chieh Ting Yeh, Yufei Liu, May Bich Nhi Lam
  • Patent number: 11762427
    Abstract: The present disclosure is drawn to covers for electronic devices. In one example, a cover for an electronic device can include an aluminum or aluminum alloy cover frame having an opening. A magnesium or magnesium alloy cover panel supported by the aluminum or aluminum alloy cover frame within or over the opening. A protective coating can be over a surface of the aluminum or aluminum alloy cover frame and a surface of the magnesium or magnesium alloy cover panel. A chamfered edge can include a chamfer at an edge of the aluminum or aluminum alloy cover frame. The chamfer can expose the aluminum or aluminum alloy cover frame beneath the protective coating, and the chamfer at the same time does not expose the magnesium or magnesium alloy cover panel.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: September 19, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Ting Wu, Ya-Ting Yeh, Chih-Hsiung Liao
  • Publication number: 20230290861
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11735660
    Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Ting-Yeh Chen, Chii-Horng Li, Feng-Cheng Yang
  • Publication number: 20230258912
    Abstract: A photographing lens system includes, in order from an object side to an image side along an optical path, a front lens group and a rear lens group. The front lens group includes four lens elements. The rear lens group includes four lens elements. A second lens element counted from the image side in the front lens group has negative refractive power. An image-side surface of a first lens element counted from the image side in the front lens group is convex in a paraxial region thereof. A second lens element counted from the object side in the rear lens group has negative refractive power. An object-side surface of a first lens element counted from the image side in the rear lens group is concave in a paraxial region thereof. At least one lens element in the rear lens group has at least one lens surface being aspheric.
    Type: Application
    Filed: May 18, 2022
    Publication date: August 17, 2023
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting YEH, Tzu-Chieh KUO
  • Publication number: 20230253494
    Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.
    Type: Application
    Filed: June 22, 2022
    Publication date: August 10, 2023
    Inventors: Kuo-Hsuan Lo, Chien-Hao Huang, Yu-Ting Yeh, Chu-Feng Chen, Wu-Te Weng
  • Patent number: 11710792
    Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Tzu-Hsiang Hsu, Ting-Yeh Chen, Feng-Cheng Yang
  • Publication number: 20230231270
    Abstract: The present invention provides a separator formed by hydrolysis of a resin film. The resin film comprises a non-hydrolyzable organic polymer; and a hydrolyzable organic polymer being hydrolyzable by treatment with at least one of an acid aqueous solution, an alkaline aqueous solution and pure water, wherein the content of the hydrolyzable organic polymer ranges from 10 parts by weight to 70 parts by weight relative to 100 parts by weight of the resin film. The separator of the present invention has good ion conductivity and thus, is extremely suitable for use in various types of batteries.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 20, 2023
    Applicant: MICROCOSM TECHNOLOGY CO., LTD.
    Inventors: Chun-Ting Yeh, Chia Yun Wang, Sih-Ci Jheng
  • Publication number: 20230228973
    Abstract: An imaging optical system lens assembly includes six lens elements, which is, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element has negative refractive power, the object-side surface of the first lens element is concave in a paraxial region thereof, the image-side surface of the first lens element is convex in a paraxial region thereof. The second lens element has positive refractive power, the object-side surface of the second lens element is convex in a paraxial region thereof, the image-side surface of the second lens element is concave in a paraxial region thereof. The fifth lens element has positive refractive power.
    Type: Application
    Filed: December 2, 2022
    Publication date: July 20, 2023
    Inventors: Kuan-Ting YEH, Meng-Kuan CHO, Cheng-Yu TSAI
  • Publication number: 20230205165
    Abstract: The present disclosure discloses a servo motor and an encoder calibration method. The encoder calibration method includes: calculating a gain error, an offset error and a phase error, by an error calculation block, according to a first signal and a second signal output by an encoder; calculating at least one gain calibration parameter, at least one offset calibration parameter and at least one phase calibration parameter, by the error calibration block, according to the gain error, the offset error and the phase error; and calibrating sequentially, by the encoder, the gain, the offset and the phase of the first signal and the second signal according to the at least one gain calibration parameter, the at least one offset calibration parameter and the at least one phase calibration parameter, wherein performing at least one gain calibration and offset calibration after the phase calibration is completed.
    Type: Application
    Filed: April 4, 2022
    Publication date: June 29, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Kai CHIU, Bo-Ting YEH, Tsan-Huang CHEN
  • Patent number: 11688794
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230197562
    Abstract: A chip device is provided. The chip device includes a substrate, at least one chip, a sealing component, a heat-conducting medium, a barrier, and a heat dissipation device. The at least one chip is disposed over a first surface of the substrate and has a heat transfer surface. The sealing component covers the at least one chip and has a heat transfer area thermal contacting the heat transfer surface of the at least one chip. The heat-conducting medium is disposed over the heat transfer area of the sealing component. The barrier is disposed around and blocks the heat-conducting medium. The heat dissipation device is disposed over the heat transfer area of the sealing component and on the heat-conducting medium. The chip device can block the heat-conducting medium through the barrier to prevent the heat-conducting medium from overflowing or losing between the sealing component and the heat dissipation device.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 22, 2023
    Inventors: Chi-Ting YEH, Ya Hui CHEN
  • Publication number: 20230189465
    Abstract: The present disclosure is drawn to covers for electronic, devices, methods of making the covers, and electronic devices, in one example, described herein Is a cover for an electronic device comprising: a substrate; a micro-arc oxidation layer applied on at least one surface of the substrate; and a dyeing layer on the micro-arc oxidation layer, wherein the dyeing layer comprises: from about 3 to about 10 wt% wafer based dyes based on the total weight of the dyeing layer; and from about 0.3 wt % to about 2 wt% surfactant based on the total weight of the dyeing layer.
    Type: Application
    Filed: May 13, 2020
    Publication date: June 15, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Ting Wu, Ya-Ting Yeh, Chi Hao Chang
  • Publication number: 20230178593
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.
    Type: Application
    Filed: June 6, 2022
    Publication date: June 8, 2023
    Inventors: Wei-Ting Yeh, Hung-Yu Yen, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20230168208
    Abstract: A surface inspection system for foil article is disclosed. The surface inspection system comprises a box having a top long narrow opening and a bottom long narrow opening, a bridge interface, a first light source, a second light source, a first modular camera device having a first camera, and a second modular camera device having a second camera. In which, the first light source, the second light source, the first modular camera device, and the second modular camera device all accommodated in the box, and are coupled to a control box through the bridge interface. Particularly, this surface inspection system is allowed to be integrated in an automatic production line of a foil article like electro-forming aluminum foil (also called electronic aluminum foil), so as to achieve an in-line inspection of the surface morphology of the electro-forming aluminum foil.
    Type: Application
    Filed: November 17, 2022
    Publication date: June 1, 2023
    Inventors: FENG-TSO SUN, YI-TING YEH, FENG-YU SUN, SHIANG-EN HONG, PO-HAN CHOU, HUI-PU CHANG, YUN-YI CHEN, JYUN-TANG HUANG
  • Publication number: 20230168298
    Abstract: A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: CHIH-TING YEH, SUNG CHIH HUANG, KUN-HSIEN LIN, CHE-HAO CHUANG
  • Patent number: 11658046
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: May 23, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ting-Yeh Wu
  • Patent number: 11652362
    Abstract: An off-line uninterruptible power system and two line-interactive uninterruptible power systems are provided. The off-line uninterruptible power system and one of the line-interactive uninterruptible power systems additionally adopt a transformer for supplying an AC output, with lower voltage level than a rated output voltage, to at least one electrical device (especially those with resistive load characteristic). The other line-interactive uninterruptible power system controls its automatic voltage regulating circuit to supply an AC output, with lower voltage level than a rated output voltage, to at least one electrical device (especially those with resistive load characteristic).
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 16, 2023
    Assignee: CYBER POWER SYSTEMS, INC.
    Inventors: Lien-Hsun Ho, Shou-Ting Yeh, Jui-Hung Chou, Kai-Tsung Yang
  • Publication number: 20230132957
    Abstract: An optical photographing system includes seven lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the sixth lens element is convex in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one lens element of the optical photographing system has at least one inflection point.
    Type: Application
    Filed: November 30, 2021
    Publication date: May 4, 2023
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Jin Sen WANG, Kuo-Jui WANG, Kuan-Ting YEH, Tzu-Chieh KUO