Patents by Inventor Tomio Iwasaki

Tomio Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090316292
    Abstract: A magnetoresistive head is provided with high reliability and produced at a high yield rate. The magnetoresistive head includes a lower magnetic shield layer, an upper magnetic shield layer, a magnetoresistive effect film, and means for causing a current to flow in the direction of the thickness of the magnetoresistive effect film. The magnetoresistive effect film is provided between the lower magnetic shield layer and the upper magnetic shield layer. The magnetoresistive effect film is composed of a fixed layer, a non-magnetic layer, an insulating barrier layer and a free layer. The four layers of the magnetoresistive effect film are formed in this order. The insulating barrier layer is an oxide layer containing at least one of titanium and nickel.
    Type: Application
    Filed: February 9, 2009
    Publication date: December 24, 2009
    Inventor: Tomio IWASAKI
  • Patent number: 7608899
    Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate lectrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: October 27, 2009
    Assignee: Renesas Technology Corporation
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Publication number: 20090256261
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 7586390
    Abstract: A bulk acoustic wave resonator which has excellent elasticity and high electromechanical energy conversion efficiency. A bulk acoustic wave resonator comprises a substrate, a lower electrode formed on the substrate, an interlayer formed on the lower electrode layer, a piezoelectric layer formed on the interlayer, and an upper electrode layer formed on the piezoelectric layer.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: September 8, 2009
    Assignee: Hitachi Media Electronics Co., Ltd.
    Inventors: Hisanori Matsumoto, Tomio Iwasaki, Kengo Asai, Nobuhiko Shibagaki
  • Publication number: 20090174061
    Abstract: To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or Ti compound film and a Ni film (or a Cu film) is interposed between the Ti film or Ti compound film formed on a silicon or silicon oxide film, and the Ni film (or the Cu film) to be connected to solder. Further, to prevent peeling-off at the interface between the Ti film or Ti compound film and the silicon oxide film, the Cr film is formed in a larger area than the Ti film or Ti compound film.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 9, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiro NAKA, Tomio Iwasaki, Hidekazu Okuda, Yuji Fujii
  • Publication number: 20090154029
    Abstract: A magnetic reproduction head includes a lower magnetic shield layer, an upper magnetic shield layer, a magnetoresistive film formed between the lower and the upper magnetic shield layers, a refill film in an element height direction disposed in contact with a surface opposite a floating surface of the magnetoresistive film, and a refill film in a track width direction disposed on a side wall surface of the magnetoresistive film. The magnetoresistive film is a tunneling magnetoresistive film including a free layer, an insulating barrier layer, and a fixed layer. The insulating barrier layer is one of a magnesium oxide film, an aluminum oxide film, and a titanium oxide film which contains at least one of nitrogen and silicon.
    Type: Application
    Filed: November 17, 2008
    Publication date: June 18, 2009
    Inventor: Tomio IWASAKI
  • Patent number: 7537858
    Abstract: The present invention provides a catalyst structure of high catalytic activity and a fuel cell of high cell output. The catalyst structure comprises a conductive film and catalyst particles formed on the conductive film wherein the difference between lattice constant of a material constituting the conductive film and that of a material constituting the catalyst particles is not more than 16%, and preferably not less than 3%.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: May 26, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura
  • Patent number: 7534507
    Abstract: Embodiments of the invention are directed to a medium which provides high media S/N and good corrosion resistance. According to one embodiment, in a perpendicular magnetic recording medium at least comprising a soft-magnetic underlayer, a seed layer, an intermediate layer, a magnetic recording layer and an overcoat layer which are stacked over a substrate in order, the magnetic recording layer has a granular structure which includes many columnar grains of CoCrPt alloy and a grain boundary layer containing an oxide, the seed layer is made of TaNi alloy or TaTi alloy and the intermediate layer is made of Ru or Ru alloy which contains 80 at. % Ru or more.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: May 19, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Reiko Arai, Yoshiyuki Hirayama, Yuzuru Hosoe, Tomio Iwasaki, Yoko Ogawa, Ikuko Takekuma
  • Publication number: 20090108420
    Abstract: A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 30, 2009
    Inventors: Yasutaka OKURA, Tomio IWASAKI, Takeshi TERASAKI
  • Patent number: 7507985
    Abstract: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: March 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideyuki Matsuoka, Norikatsu Takaura
  • Publication number: 20080297947
    Abstract: The present invention provides a magnetic disk in a discrete track medium and a patterned medium, which prevents the loss of the magnetically recorded data when a head of a magnetic disk device contacts the magnetic disk, and a manufacturing method thereof. A magnetic disk has a protrusion as a non-magnetic member formed on a disk surface to prevent a head from being in contact with a recording section. When the protrusion formed in a disk substrate collides against the head, the protrusion 7 does not collapse, and accordingly, the recording layer is not damaged. Alternatively, concave and convex portions are formed on the substrate surface to use the convex portion as the protrusion.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Inventors: Yasutaka Okura, Tomio Iwasaki
  • Patent number: 7459786
    Abstract: A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing through the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: December 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hiromi Shimazu, Tomio Iwasaki, Hiroyuki Ohta, Kensuke Ishikawa, Osamu Inoue, Takayuki Oshima
  • Publication number: 20080188043
    Abstract: After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
    Type: Application
    Filed: December 26, 2007
    Publication date: August 7, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Norio Ishitsuka, Nobuyoshi Hattori, Tomio Iwasaki
  • Publication number: 20080144218
    Abstract: A patterned magnetic medium includes: a substrate; a soft magnetic underlying film, a nonmagnetic film, an intermediate film and a recording layer which are formed on a principal surface of the substrate; a first protective film formed in contact with the recording film; a second protective film formed in contact with the first protective film; and a third protective film formed in contact with the second protective film. Moreover, the recording layer has a pattern structure formed by making a magnetic film come into contact with a concavo-convex pattern of a nonmagnetic material. The first protective film and the third protective film include carbon as the main constituent element and the second protective film is a wet-coated polymer film. High adhesion between carbon and the wet-coated polymer film can prevent peeling off and the wet-coated polymer film as a cushioning material absorbs impact.
    Type: Application
    Filed: December 14, 2007
    Publication date: June 19, 2008
    Inventor: Tomio Iwasaki
  • Patent number: 7358578
    Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: April 15, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Publication number: 20080061384
    Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
    Type: Application
    Filed: November 7, 2007
    Publication date: March 13, 2008
    Applicant: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Publication number: 20080036090
    Abstract: Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 14, 2008
    Inventors: Tomio Iwasaki, Hideo Miura
  • Publication number: 20080006851
    Abstract: In a non-volatile phase-change memory comprising: an interlayer dielectric film and a plug formed on one main surface side of a silicon substrate; a phase-change film which can take a different electric resistivity depending on a phase change and is provided on surfaces of the interlayer dielectric film and the plug; and an upper electrode film formed on an upper surface of the phase-change film, a relation between a film thickness of the phase-change film and an amount of protrusion of the upper electrode film from the plug is set to 0.3?L/T?1. Thus, a density of current flowing through the phase-change film near the outer periphery of the plug is reduced, thereby suppressing migration and enabling rewriting with low energy. Accordingly, a reliable non-volatile phase-change memory can be achieved.
    Type: Application
    Filed: July 6, 2007
    Publication date: January 10, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Hiroshi Moriya, Tomio Iwasaki
  • Publication number: 20070241320
    Abstract: A thin film electron source comprising a substrate, a lower electrode formed on one main face of said substrate, an insulation layer formed in contact with said lower electrode and an upper electrode formed in contact with said insulation layer. The upper electrode comprises a first under-layer, a second under-layer, an intermediate layer and a surface layer laminated from the insulation layer side. A main material of the first under-layer is IrO2 or RuO2; a main material of the second under-layer is Ir or Ru, and a main material of the surface layer is a member selected from the group consisting of Au and Ag.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 18, 2007
    Inventor: Tomio Iwasaki
  • Patent number: 7279739
    Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: October 9, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki