Patents by Inventor Tomio Iwasaki

Tomio Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060180852
    Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 17, 2006
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki
  • Publication number: 20060183634
    Abstract: An object of the present invention is to provide a catalyst structure of high catalytic activity and highly functional exhaust gas treatment system. The catalyst structure of the present invention is provided with a carrier and catalyst particles formed on the carrier, wherein a difference in lattice constant between the carrier material and the catalyst particle material is 16% or less, preferably 1% to 16%.
    Type: Application
    Filed: February 14, 2006
    Publication date: August 17, 2006
    Inventor: Tomio Iwasaki
  • Patent number: 7084477
    Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: August 1, 2006
    Assignees: Hitachi, Ltd., Trecenti Technologies, Inc.
    Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
  • Patent number: 7064437
    Abstract: There is provided a semiconductor device having high reliability, high yield, and such a interconnection structure as short hardly occurs. The semiconductor device comprises a semiconductor substrate, metal conductors formed on a side of a main face of the substrate which metal conductors contain aluminum as main constituent thereof and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: June 20, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Publication number: 20060127703
    Abstract: Embodiments of the invention provide a medium which provides high media S/N and good corrosion resistance. According to one embodiment, in a perpendicular magnetic recording medium at least comprising a soft-magnetic underlayer, a seed layer, an intermediate layer, a magnetic recording layer and an overcoat layer which are stacked over a substrate in order, the magnetic recording layer has a granular structure which consists of many columnar grains of CoCrPt alloy and a grain boundary layer containing an oxide, the seed layer is made of TaNi alloy or TaTi alloy and the intermediate layer is made of Ru or Ru alloy which contains about 80 at. % Ru or more.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 15, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Ikuko Takekuma, Reiko Arai, Yoko Ogawa, Yoshiyuki Hirayama, Yuzuru Hosoe, Tomio Iwasaki
  • Publication number: 20060088734
    Abstract: Embodiments of the invention are directed to a medium which provides high media S/N and good corrosion resistance. According to one embodiment, in a perpendicular magnetic recording medium at least comprising a soft-magnetic underlayer, a seed layer, an intermediate layer, a magnetic recording layer and an overcoat layer which are stacked over a substrate in order, the magnetic recording layer has a granular structure which includes many columnar grains of CoCrPt alloy and a grain boundary layer containing an oxide, the seed layer is made of TaNi alloy or TaTi alloy and the intermediate layer is made of Ru or Ru alloy which contains 80 at. % Ru or more.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 27, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Reiko Arai, Yoshiyuki Hirayama, Yuzuru Hosoe, Tomio Iwasaki, Yoko Ogawa, Ikuko Takekuma
  • Publication number: 20060087921
    Abstract: A phase change memory comprises a phase-change recording layer for recording information through changing between a crystal phase and an amorphous phase; and a means for applying a tensile strain onto the phase-change recording layer, thereby providing the memory having high reliability, as well as, high tolerance or durability against repetitive rewriting operation.
    Type: Application
    Filed: August 31, 2005
    Publication date: April 27, 2006
    Inventor: Tomio Iwasaki
  • Patent number: 7030493
    Abstract: Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura
  • Patent number: 7012312
    Abstract: A highly reliable semiconductor device having a multilayer structure including an insulating film, an adjacent conductive film, and a main conductive film in which adhesive fractures, voids and disconnections are unlikely to occur. Regarding main constituent elements of the adjacent conductive film and the main conductive film, lattice mismatching is made small, the melting point the adjacent conductive film is set to be not less than 1.4 times that of the main constituent element of the main conductive film, the adjacent conductive film contains at least one different kind of element, the difference between the atomic radius of an added element and that the atomic radius the adjacent conductive film is set to be not more than 10%, and/or bond energy between the added element and silicon (Si) is not less than 1.9 times that of the main constituent element of the adjacent conductive film and silicon (Si).
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: March 14, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura, Isamu Asano
  • Patent number: 7009279
    Abstract: In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: March 7, 2006
    Assignees: Hitachi, Ltd., Trecenti Technologies, Inc.
    Inventors: Shingo Nasu, Tomio Iwasaki, Hiroyuki Ohta, Yukihiro Kumagai, Shuji Ikeda
  • Publication number: 20060043605
    Abstract: To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or Ti compound film and a Ni film (or a Cu film) is interposed between the Ti film or Ti compound film formed on a silicon or silicon oxide film, and the Ni film (or the Cu film) to be connected to solder. Further, to prevent peeling-off at the interface between the Ti film or Ti compound film and the silicon oxide film, the Cr film is formed in a larger area than the Ti film or Ti compound film.
    Type: Application
    Filed: June 29, 2005
    Publication date: March 2, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Yasuhiro Naka, Tomio Iwasaki, Hidekazu Okuda, Yuji Fujii
  • Publication number: 20060019124
    Abstract: A perpendicular magnetic recording medium, comprises: a substrate; a soft-magnetic underground layer formed on one main surface of the substrate; a non-magnetic layer formed on the soft-magnetic underground layer; an intermediate layer formed on the non-magnetic layer; and a perpendicular recording layer formed on the intermediate layer, wherein an addition element is contained within the intermediate layer, for improving flatness of the surface thereof, thereby having high reliability and high functions, as well as, a magnetic recording apparatus having high reliability and high performances.
    Type: Application
    Filed: July 22, 2005
    Publication date: January 26, 2006
    Inventors: Tomio Iwasaki, Yuzuru Hosoe
  • Patent number: 6989599
    Abstract: A reliable semiconductor device is provided with a layered interconnect structure that may develop no problem of voids and interconnect breakdowns, in which the layered interconnect structure includes a conductor film and a neighboring film so layered on a semiconductor substrate that the neighboring film is in contact with the conductor film.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: January 24, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura
  • Publication number: 20060006543
    Abstract: A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing thorough the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.
    Type: Application
    Filed: June 17, 2005
    Publication date: January 12, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Hiromi Shimazu, Tomio Iwasaki, Hiroyuki Ohta, Kensuke Ishikawa, Osamu Inoue, Takayuki Oshima
  • Publication number: 20050269662
    Abstract: To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 8, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Norio Ishitsuka, Jun Tanaka, Tomio Iwasaki, Hiroyuki Ohta
  • Patent number: 6965140
    Abstract: It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: November 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yukihiro Kumagai, Hideo Miura, Hiroyuki Ohta, Tomio Iwasaki, Isamu Asano
  • Patent number: 6960832
    Abstract: In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: November 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hiromi Shimazu, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shuji Ikeda
  • Patent number: 6943076
    Abstract: Gate insulation films each containing titanium oxide as a primary constituent material are formed on one major surface of a semiconductor substrate. Gate electrode films are formed in contact with the gate insulation films. The gate electrode films contain ruthenium oxide or alternatively iridium oxide as a primary constituent material. In order to prevent electrically conductive elements from diffusing into titanium oxide of the gate insulation films, ruthenium oxide or iridium oxide is effectively used as a primary constituent material of the gate electrodes. A semiconductor device can be realized in which occurrence of a leak current is suppressed by increasing a physical film thickness while sustaining desired dielectric characteristic.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 13, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura, Hiroyuki Ohta, Hiroshi Moriya
  • Patent number: 6940118
    Abstract: A semiconductor device has a gate dielectric film formed of zirconium oxide or hafnium oxide as a chief material and a gate electrode film in contact with the gate dielectric film on one principal surface side of a silicon substrate. The gate dielectric film contains an addition element to prevent diffusion of oxygen.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: September 6, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Publication number: 20050179133
    Abstract: A semiconductor device provided with a mechanism for recording information is intended to provide a highly reliable one time programmable memory and to provide one time programmable memories at a high yield. In a one time programmable memory, a state in which the electrical resistance is high is varied to another state in which it is low by silicifying a metal with silicon and matching the high resistance state (a metal/silicon separated state) and the low resistance state (a silicide state) to 0 and 1, respectively, wherein there is used an underlayer material which reduces the interfacial energy in the interface with the silicide layer, which constitutes the low resistance state.
    Type: Application
    Filed: October 29, 2004
    Publication date: August 18, 2005
    Inventors: Tomio Iwasaki, Hiroshi Moriya