Patents by Inventor Tomio Iwasaki

Tomio Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7279769
    Abstract: To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Norio Ishitsuka, Jun Tanaka, Tomio Iwasaki, Hiroyuki Ohta
  • Publication number: 20070206325
    Abstract: The present invention provides a highly reliable patterned medium without generating an error in recording and reproduction, and a magnetic disc memory device using the same. The patterned medium has a substrate, a soft magnetic layer, a non-magnetic layer, an intermediate layer and a recording layer. The recording layer has a pattern structure of a non-magnetic material and a magnetic material, and the Young's modulus of the non-magnetic material is larger than the Young's modulus of the magnetic material.
    Type: Application
    Filed: January 18, 2007
    Publication date: September 6, 2007
    Inventor: Tomio Iwasaki
  • Publication number: 20070187823
    Abstract: An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
    Type: Application
    Filed: April 13, 2007
    Publication date: August 16, 2007
    Inventors: Naotaka Tanaka, Tomio Iwasaki, Hideo Miura, Yasuyuki Nakajima, Tomoo Matsuzawa
  • Patent number: 7253103
    Abstract: Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: August 7, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura
  • Publication number: 20070170413
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Application
    Filed: May 9, 2005
    Publication date: July 26, 2007
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 7241685
    Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: July 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hideo Miura, Shinji Nishihara, Masashi Sahara
  • Patent number: 7217971
    Abstract: Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: May 15, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Publication number: 20070096189
    Abstract: In order to supply a semiconductor device having high-reliability, there are used a first capacitor electrode, a capacitor insulating film formed in contact with the first capacitor electrode and mainly composed of titanium oxide, and a second capacitor electrode formed in contact with the capacitor insulating film, and there is used a conductive oxide film mainly composed of ruthenium oxide or iridium oxide for the first capacitor electrode and the second capacitor electrode. Alternatively, there is used a gate insulating film having a titanium silicate film and titanium oxide which suppress leakage current.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 3, 2007
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Patent number: 7180143
    Abstract: A semiconductor device constitutes an electric field effect type transistor having a semiconductor substrate, a gate insulating layer formed on the substrate and a gate electrode formed on the gate insulating layer. The gate insulating layer is mainly formed of silicon oxynitride (SiON) and a strain state of the gate insulating layer is a compressed strain state.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki, Hiroshi Moriya
  • Publication number: 20060289850
    Abstract: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.
    Type: Application
    Filed: September 1, 2006
    Publication date: December 28, 2006
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideyuki Matsuoka, Norikatsu Takaura
  • Publication number: 20060267710
    Abstract: A bulk acoustic wave resonator which has excellent elasticity and high electromechanical energy conversion efficiency. A bulk acoustic wave resonator comprises a substrate, a lower electrode formed on the substrate, an interlayer formed on the lower electrode layer, a piezoelectric layer formed on the interlayer, and an upper electrode layer formed on the piezoelectric layer.
    Type: Application
    Filed: February 2, 2006
    Publication date: November 30, 2006
    Inventors: Hisanori Matsumoto, Tomio Iwasaki, Kengo Asai, Nobuhiko Shibagaki
  • Publication number: 20060266992
    Abstract: Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer comprising an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 30, 2006
    Inventors: Yuichi Matsui, Tomio Iwasaki, Norikatsu Takaura, Kenzo Kurotsuchi
  • Patent number: 7141840
    Abstract: A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the silicon substrate, a gate electrode formed by being stacked on the gate dielectric film and a diffusion layer containing arsenic and phosphorus. Both of the concentration of the highest concentration portion of arsenic and the concentration of the highest concentration portion of phosphorus are each at 1026 atoms/m3 or more and 1027 atoms/m3 or less, and the depth of the highest concentration portion of phosphorus from the surface of the silicon substrate is less than the depth of the highest concentration portion of arsenic.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: November 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tomio Iwasaki, Norio Ishitsuka, Hideo Miura
  • Patent number: 7135732
    Abstract: In order to supply a semiconductor device having high-reliability, there are used a first capacitor electrode, a capacitor insulating film formed in contact with the first capacitor electrode and mainly composed of titanium oxide, and a second capacitor electrode formed in contact with the capacitor insulating film, and there is used a conductive oxide film mainly composed of ruthenium oxide or iridium oxide for the first capacitor electrode and the second capacitor electrode. Alternatively, there is used a gate insulating film having a titanium silicate film and titanium oxide which suppress leakage current.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 14, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Patent number: 7126149
    Abstract: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: October 24, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideyuki Matsuoka, Norikatsu Takaura
  • Publication number: 20060226555
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: June 9, 2006
    Publication date: October 12, 2006
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20060223268
    Abstract: An object of the present invention is to provide a phase-change random access memory which hardly causes the peeling of a phase-change film in a production process. In the present invention, the surface of an insulating film around the phase-change film is positioned to a more substrate side than an interface between the insulating film and the phase-change film on the insulating film is.
    Type: Application
    Filed: January 10, 2006
    Publication date: October 5, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Hiroshi Moriya, Tomio Iwasaki
  • Publication number: 20060214254
    Abstract: To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 28, 2006
    Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
  • Publication number: 20060183634
    Abstract: An object of the present invention is to provide a catalyst structure of high catalytic activity and highly functional exhaust gas treatment system. The catalyst structure of the present invention is provided with a carrier and catalyst particles formed on the carrier, wherein a difference in lattice constant between the carrier material and the catalyst particle material is 16% or less, preferably 1% to 16%.
    Type: Application
    Filed: February 14, 2006
    Publication date: August 17, 2006
    Inventor: Tomio Iwasaki
  • Publication number: 20060183633
    Abstract: An object of the present invention is to provide a catalyst structure of high catalytic activity and fuel cell of high cell output. The catalyst structure of the present invention includes a carrier and catalyst particles formed on the carrier, wherein a difference in lattice constant between the carrier material and the catalyst particle material is 16% or less, preferably 1% to 16%.
    Type: Application
    Filed: February 13, 2006
    Publication date: August 17, 2006
    Inventor: Tomio Iwasaki