Patents by Inventor Tomoko Matsudai

Tomoko Matsudai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296478
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and first and second control electrodes in a trench of the semiconductor part. The first and second control electrodes are arranged along a front surface of the semiconductor part. The semiconductor part includes first and third layers of a first-conductivity-type, and the second and fourth layer of a second-conductivity-type. The second layer is provided between the first layer and the second electrode. Between the second layer and the second electrode, the third and fourth layers are provided apart from the first layer with first and second portions of the second layer interposed, respectively. The first portion of the second layer has a first thickness in a second direction from the first electrode toward the second electrode. The second portion of the second layer has a second thickness in the second direction larger than the first thickness.
    Type: Application
    Filed: September 14, 2020
    Publication date: September 23, 2021
    Inventors: Takeshi SUWA, Tomoko MATSUDAI, Yoko IWAKAJI
  • Publication number: 20210296477
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part includes first to third layers. The first electrode is provided on a back surface of the semiconductor part. The second electrode is provided on a front surface of the semiconductor part. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The third layer of the second conductivity type is provided between the second layer and the second electrode. The second electrode includes a buried contact portion and a surface contact portion. The buried contact portion extends into the second layer from the front surface of the semiconductor part and contacts the second layer. The surface contact portion contacts the third layer at the front surface of the semiconductor part.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 23, 2021
    Inventors: Tomoko Matsudai, Hiroko Itokazu, Keiko Kawamura, Yoko Iwakaji, Kaori Fuse
  • Publication number: 20210296459
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko IWAKAJI, Tomoko MATSUDAI, Keiko KAWAMURA
  • Publication number: 20210296495
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, first to third control electrodes inside the semiconductor part, and first to third interconnects. The first and second control electrodes are arranged along a front surface of the semiconductor part. The third control electrodes are provided between the first electrode and the first and second electrodes, respectively. The first and second interconnect are electrically connected to the first and second control electrodes, respectively. The third interconnect is electrically connected to the third control electrodes. The semiconductor layer includes first and third layers of a first conductivity type and a second layer of a second conductivity type. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The second layer faces the first and second control electrodes via insulating portions.
    Type: Application
    Filed: September 8, 2020
    Publication date: September 23, 2021
    Inventors: Takeshi SUWA, Tomoko MATSUDAI, Yoko IWAKAJI
  • Publication number: 20210296476
    Abstract: A semiconductor device according to an embodiment including a semiconductor layer having a first plane and a second plane, the semiconductor layer including: a first trench on the first plane; a second trench on the second plane; a first conductivity first semiconductor region; a second conductivity type second semiconductor region between the first semiconductor region and the first plane; a first conductivity type third semiconductor region between the second semiconductor region and the first plane; a second conductivity type fourth semiconductor region between the third semiconductor region and the first plane; and a first conductivity type fifth semiconductor region provided between the second trench and the third semiconductor region in contact with the second trench; a first gate electrode in the first trench; a second gate electrode in the second trench; a first electrode on the first plane; and a second electrode on the second plane.
    Type: Application
    Filed: August 17, 2020
    Publication date: September 23, 2021
    Inventors: Tomoko Matsudai, Yoko Iwakaji
  • Publication number: 20210296310
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided in a trench of the semiconductor part between the semiconductor part and the second electrode. The semiconductor part includes first to third layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The second layer is connected to the second electrode. The third layer of the second conductivity type is provided between the second layer and the control electrode. The third layer includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second layer. The third layer contacts the second electrode, and is electrically connected to the second electrode.
    Type: Application
    Filed: August 6, 2020
    Publication date: September 23, 2021
    Inventors: Hiroko Itokazu, Tomoko Matsudai, Yoko Iwakaji, Takako Motai
  • Publication number: 20210296475
    Abstract: A semiconductor device of one embodiment including: a semiconductor layer with first and second planes, first and second trenches, a third trench beside the first trench, a fourth trench beside the second trench, and first to fourth semiconductor regions; first to fourth gate electrodes in the first to fourth trenches, respectively; a first electrode on the first plane, a first contact area with the semiconductor layer between the first trench and the third trench being larger than a second contact area with the semiconductor layer between the third trench and the fourth trench, a third contact area with the semiconductor layer between the second trench and the fourth trench being larger than the second contact area; a second electrode on the second plane; a first gate electrode pad connected to the first and second gate electrodes; and a second gate electrode pad connected to the third and fourth gate electrodes.
    Type: Application
    Filed: August 10, 2020
    Publication date: September 23, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko Iwakaji, Tomoko Matsudai
  • Publication number: 20210288143
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween; first and second control electrodes each in a trench at the frontside of the semiconductor part. The semiconductor part includes first to sixth layers. The first and third layers are of a first conductivity type. Other layers are of a second conductivity type. The first layer extends between the first electrode at the backside and the second electrode at the frontside. The second layer is provided between the first layer and the second electrode. The third and fourth layers each are selectively provided between the second layer and the second electrode. The fifth layer is provided between the first layer and the first electrode. The sixth layer is provided between the first layer and the second control electrode. The sixth layer extends along an insulating film between the semiconductor part and the second control electrode.
    Type: Application
    Filed: August 27, 2020
    Publication date: September 16, 2021
    Inventors: Yoko Iwakaji, Tomoko Matsudai
  • Patent number: 11101375
    Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11063130
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Keiko Kawamura
  • Patent number: 10985268
    Abstract: A semiconductor device includes a semiconductor substrate including first and second surfaces, and a first semiconductor layer of a first conductivity type, a first electrode on the first surface, a first control electrode that is inwardly from the first surface and electrically insulated from the semiconductor substrate and the first electrode, a second control electrode that is inwardly from the first surface, electrically insulated from the semiconductor substrate and the first electrode via a fourth insulating film, and biased independently from the first control electrode, a third control electrode on the second surface and electrically insulated from the semiconductor substrate, and a second electrode on the second surface and electrically connected to the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 20, 2021
    Assignees: KABUSH1 KI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Matsudai, Yoko Iwakaji
  • Publication number: 20210091193
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Application
    Filed: February 14, 2020
    Publication date: March 25, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko IWAKAJI, Tomoko MATSUDAI, Keiko KAWAMURA
  • Publication number: 20210091072
    Abstract: A semiconductor device of the embodiment includes a semiconductor layer including a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, a first trench, and a second trench, a first gate electrode in the first trench; a second gate electrode in the second trench; a first electrode on a first face side; a second electrode on a second face side; a first electrode pad connected to the first gate electrode; and a second electrode pad connected to the second gate electrode. The semiconductor device includes a first region including the first semiconductor region; a second region including the second semiconductor region; and a third region provided between the first region and the second region, the third region having a density of the second trench higher than that of the first region.
    Type: Application
    Filed: February 14, 2020
    Publication date: March 25, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko MATSUDAI, Yoko Iwakaji
  • Publication number: 20210083060
    Abstract: A semiconductor device includes a semiconductor part, a first electrode at a back surface of the semiconductor part; a second electrode at a front surface of the semiconductor part; third and fourth electrodes provided between the semiconductor part and the second electrode. The third and fourth electrodes are arranged in a first direction along the front surface of the semiconductor part. The third electrode is electrically insulated from the semiconductor part by a first insulating film. The third electrode is electrically insulated from the second electrode by a second insulating film. The fourth electrode is electrically insulated from the semiconductor part by a third insulating film. The fourth electrode is electrically isolated from the third electrode. the third and fourth electrodes extend into the semiconductor part. The fourth electrode includes a material having a larger thermal conductivity than a thermal conductivity of a material of the third electrode.
    Type: Application
    Filed: March 9, 2020
    Publication date: March 18, 2021
    Inventors: Takeshi Suwa, Tomoko Matsudai, Yoko Iwakaji
  • Publication number: 20210066480
    Abstract: A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.
    Type: Application
    Filed: February 26, 2020
    Publication date: March 4, 2021
    Inventors: Keiko KAWAMURA, Tomoko MATSUDAI, Yoko IWAKAJI
  • Patent number: 10903348
    Abstract: A semiconductor device includes a semiconductor body including first to fourth semiconductor layers. The second semiconductor layer of second conductivity type is provided on the first semiconductor layer of first conductivity type; the third semiconductor layer of first conductivity type is provided selectively on the second semiconductor layer; and the fourth semiconductor layer of second conductivity type is provided selectively on the second semiconductor layer. The semiconductor device further includes first and second control electrodes. The first and second control electrodes are provided inside the semiconductor body and oppose the second semiconductor layer with first and second insulating films interposed, respectively, and are arranged alternately with a third insulating layer interposed. The first control electrode contacts the third insulating layer at a first surface thereof, and the second control electrode contacts the third insulating layer at a second surface opposite to the first surface.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 26, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 10903346
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane; an emitter electrode provided on a first plane side of the semiconductor layer; a collector electrode provided on a second plane side of the semiconductor layer; a first gate electrode pad provided on the first plane side; a second gate electrode pad provided on the first plane side; a cell region including a first trench provided in the semiconductor layer and a first gate electrode that is provided in the first trench and is connected to the first gate electrode pad; and a cell end region that is adjacent to the cell region and includes a second trench provided in the semiconductor layer and a second gate electrode which is provided in the second trench and is connected to the second gate electrode pad.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 26, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Tsuneo Ogura
  • Patent number: 10840365
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: November 17, 2020
    Assignees: Kyushu Institute of Technology, Mitsubishi Electric Corporation, Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Katsumi Satoh, Tomoko Matsudai
  • Patent number: 10811524
    Abstract: A semiconductor circuit of an embodiment includes semiconductor device and a control circuit. The semiconductor device includes a semiconductor layer that has a first region of a first-conductivity type, a second region of a second-conductivity type, a third region of the first-conductivity type, fourth region of the second-conductivity type, first and second trench, first and second gate electrode, a first gate insulating film in contact with the fourth region, and a second gate insulating film spaced away from the fourth region. The semiconductor device includes a first gate electrode pad connected to the first gate electrode, and a second gate electrode pad connected to the second gate electrode. Prior to changing a first gate voltage from a turn-ON voltage to a turn-OFF voltage, a second gate voltage changed from a first voltage to a second voltage. The second voltage is a negative voltage when the first-conductivity type is p-type.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Takeshi Suwa
  • Publication number: 20200303527
    Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
    Type: Application
    Filed: September 17, 2019
    Publication date: September 24, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa