Abstract: A questionless case-based knowledge base suitable for access by an intelligent search engine and an associated method for constructing the same from pre-existing on-line documentation. A case structure for questionless cases is determined. The determined case structure includes a first field for containing a title for a case, a second field for containing a description of the case and a third field for containing a solution for the case. On-line documentation having information directed to a plurality of topics, each of which includes a title portion and a contents portion, is then provided. The information directed to each of the plurality of topics is then reconfigured into the determined case structure such that the title portion of each topic is configured as a first field of a corresponding case and the contents portion of each topic is configured as a second field of the corresponding case.

Abstract: A single piece soft foldable IOL having open loop haptics of specific thickness and geometry. The unique geometry provides an IOL with improved fixation and centration.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: A system in which a case-based search engine is integrated into a "help" database. The help database may be organized in a predetermined manner and converted by a computer program into a case-based format. An operator of a "help" program (e.g., a user who desires on-line help) may request a case-based search of the case-base using case-based methods. The case-based search provides a set of likely cases, i.e., help topics, from among which the operator may select the next help topic to view. The system may also present matched objects in response to the query, may respond to iterative refinement of the query (in similar manner to known iterative case-based methods) and may order matched objects by quality of match.

Abstract: A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas, such as silane for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, a slurry supply system delivering a slurry to the polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly; and an optical measurement system measuring film thickness at multiple different locations on the wafer face while the wafer is under a liquid, wherein drying of the wafer is avoided while the measurements are taken.

Abstract: A selective etching and chemical mechanical planarization process is employed for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays. The process is employed to construct an emission grid whereby the gate structure is capable of producing a field strength at the cathode tip sufficient to generate electron emission. The gate is disposed at a location above the tip such that the gate physically intercepts the outermost lateral portions of the beam, yet does not induce a significant electrostatic outward divergence of the beam, thereby reducing the cross-section of the beam.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

Abstract: A system for polishing a semiconductor wafer, the system comprising a platen subassembly defining a polishing area; a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and means for heating the wafer while the wafer face is being polished.

Abstract: A highly accurate apparatus and method of predicting remaining capacity Q and reserve time t of a discharging battery to a selected end voltage is determined by an arrangement considering the open circuit voltage, battery voltage, battery temperature and its internal resistance. The remaining battery capacity Q is determined from the difference between the battery full charge open circuit voltage Eoc and the voltage loss due to the internal resistance of the battery IRint and the battery voltage on discharge divided by the battery temperature T, which is the temperature-corrected battery overvoltage.

Abstract: A battery charging system controls and modifies the output voltage of the charging rectifier in response to differing temperature ranges of the battery. At a low range of temperatures starting at a low temperature (e.g. within a range of 0 to 25.degree. C. to about 53.degree. C.) the rectifier voltage decreases as the temperature increases to prevent charging current from rising as the battery temperature increases. This change is performed in accord with a linear graphical slope relating the change of charging voltage to temperature. A suitable charging voltage decrease rate may be 3 mV/.degree. C./cell with a range of 1.5 mV/.degree. C./cell to 5 mV/.degree. C./cell being acceptable. Reduction of the charging voltage within this range reduces the aging effect of high temperature operation of the battery. The charging voltage applied to the battery is held at a constant value over a subsequent range of temperatures (e.g. 53.degree. C. to 75.degree. C.

Abstract: Disclosed is a method for planarizing a metal surface and forming coplanar metal and dielectric layer surfaces with a minimized degree of dishing (metal recess in an oxide cavity or trough) which results from the uneven polishing with a polishing pad. A cavity is formed in a substrate material, such as oxide, and a layer of conductive material such as metal is formed over the cavity and other surfaces of the substrate. Next, a protective layer of material such as silicon dioxide, borophosphosilicate glass (BPSG), silicon nitride, or tetraethylorthosilicate (TEOS), or any insulator or conductor which can be removed at a slower rate than the conductive layer, is formed over the metal surface, the protective layer being not as easily polished as the metal in a chemical mechanical polishing (CMP) process optimized for metal polishing. A first CMP process removes a portion of the protective layer from the underlying metal overburden.

Abstract: A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing.

Abstract: A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver inverter having an input and an output. The inverter inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: A process for forming die contacting substrate for establishing ohmic contact with the die is formed with raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. In the preferred embodiment, the substrate is formed of semiconductor material, with the raised portions being formed by etching. The arrangement may be used for establishing temporary electrical contact with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.

Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.