Abstract: A light emitting device includes a semiconductor stack, and an insulating layer partially covering the semiconductor stack. The semiconductor stack includes a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer that are stacked in sequence. A reflective layer is disposed in the insulating layer, and includes a metal reflective layer and an anti-oxidation layer stacked one on top of the other. A light emitting apparatus is also disclosed.

Abstract: A method may include obtaining a machine learning (ML) pipeline including a plurality of functional blocks within the ML pipeline. The method may also include using the ML pipeline as an input to a visualization predictor, where the visualization predictor may be trained to output one or more visualization commands based on relationships between the visualization commands and the functional blocks within the pipeline. The method may additionally include invoking the visualization commands to instantiate the ML pipeline with visualizations generated by the one or more visualization commands.

Abstract: According to an aspect of an embodiment, operations for detection of API compatibility across software versions are provided. The operations may include receiving an input associated with a software application. The operations may further include determining first information. The operations may further include extracting a set of data from one or more web-based sources based on the determined first information. The operations may further include executing a set of operations including one or more pattern searching operations on the extracted set of data to generate a compatibility result. The operations may further include controlling a display device based on the generated compatibility result. The display device may be controlled to display assistive information which informs about a compatibility of the one or more APIs or the functions used in the source code of the software application with respect to the second version of the software.

Abstract: An electronic device manufacturing system configured to obtain sensor data associated with a deposition process performed in a process chamber to deposit a film stack on a surface of a substrate. The film stack can include a known film pattern and an unknown film pattern. The manufacturing system is further configured to input the sensor data into a first trained machine-learning model to obtain a first output value of the first trained machine-learning model. The first output value can be associated with the known film pattern. The manufacturing system is further configured to input the first output value into a second trained machine-learning model to obtain a second output value of the second trained machine-learning model. The second output value can be indicative of metrology data of the known film pattern.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Abstract: Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

Abstract: A method includes extracting, from a web application programming interface (API) repository, first information associated with a plurality of web APIs and constructing an initial dataset associated with the plurality of web APIs by performing a first set of information processing operations on the extracted first information. The method further includes constructing a training dataset by performing a second set of information processing operations on the constructed initial dataset and obtaining a Machine Learning (ML) model based on the constructed training dataset. The method further includes receiving an input natural language query via an electronic user interface (UI) and providing the received input natural language query to the obtained ML model. The method further includes outputting a set of recommendation results based on the provided input natural language query to the obtained ML model. Each recommendation result includes a specific API name and a specific endpoint.

Abstract: A filling method capable of reducing medicinal liquid loss, comprising weighing stations and a liquid-dividing container. The liquid-dividing container is provided with liquid outlets; filling needles arranged side by side are correspondingly arranged above the plurality of weighing stations; the respective liquid outlets and the respective filling needles are connected by means of pipelines; and the respective pipelines are each provided with a filling pump.

Abstract: An integrated circuit includes a first buried power rail, a second buried power rail, a first power pad in a first metal layer, and a first conductive segment beneath the first metal layer. The first buried power rail and the second buried power rail are both located beneath the first metal layer. The first power pad is configured to receive a first supply voltage through at least one first via. The first conductive segment is conductively connected to the first power pad through at least one second via between the first conductive segment and the first metal layer. The first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.

Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Abstract: Provided is a method for manufacturing integrated circuit (IC) devices including the operations of forming a first metal pattern (Mx) on a semiconductor substrate, forming a first via pattern (Vx) on the first metal pattern using an area selective deposition (ASD) that includes first and second vias formed adjacent opposed edges or terminal portions of the first metal pattern, and forming a second metal pattern (Mx+1) on the first via pattern with substantially no pattern overlap to form a zero enclosure and wherein a pair of adjacent vias are separated by a distance corresponding to the smallest end-to-end metal pattern spacing permitted under a set of design rules applied during the design of the IC devices.

Abstract: A method comprises receiving vehicle data comprising information associated with a plurality of sensors of autonomous vehicle and segmenting the received vehicle data into non-public data and public data. The method further comprises partitioning the public data into a plurality of data partitions and generating a plurality of data levels of the public data. Each data level of the plurality of data levels is generated according to an access level of a plurality of access levels and includes one or more data partitions of the plurality of data partitions in an encrypted form. The method further comprises transmitting the generated plurality of data levels to a group of electronic devices. Each electronic device of the group of electronic devices retrieves, according to one of the plurality of access levels, at least a portion of the public data from the transmitted plurality of data levels.

Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram.

Abstract: According to an aspect of an embodiment, operations for trend monitoring of code repositories and related information are provided. The operations include identifying a set of repositories from a collection of repositories hosted on one or more web-based repository hosting systems and collecting repository metadata for each repository. The operations further include generating a set of topic tags by using one or more natural language processing-based methods and collecting a set of statistics associated with each of the generated set of topic tags. The operations further include generating a set of presentation data based on one or more of the identified set of repositories, the collected repository metadata, the generated set of topic tags, and the collected set of statistics. The operations further include controlling a user device to display the generated set of presentation data onto an electronic User Interface of the user device.

Abstract: Operations may include obtaining a dataset that includes a plurality of unique values and obtaining a plurality of permutations with respect to the plurality of unique values. Additionally, the operations may include, for each respective permutation, obtaining a respective overall permutation probability for the respective permutation based on masked value probabilities determined by a masked language model (MLM). Each masked value probability may be determined with respect to a respective masked version of a plurality of masked versions of the respective permutation. The operations may also include selecting a particular permutation from the plurality of permutations based on a comparison between the respective overall permutation probabilities of the plurality of permutations.

Abstract: An LED device includes an epitaxial layered structure, a current spreading layer, a first insulating layer and a reflective structure. The current spreading layer is formed on a surface of the epitaxial layered structure. The first insulating layer is formed over the current spreading layer, and is formed with at least one first through hole to expose the current spreading layer. The reflective structure is formed on the first insulating layer, extends into the first through hole, and contacts the current spreading layer. The current spreading layer is formed with at least one opening structure to expose the surface of the epitaxial layered structure.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A light-emitting diode (LED) includes a light-transmissive substrate which has a first surface, an epitaxial structure which is disposed on the first surface, a first insulation layer, and a second insulation layer. The epitaxial structure has an upper surface opposite to the first surface, and a side wall interconnecting the upper surface and the first surface. The first insulation layer covers the side wall and the upper surface. The second insulation layer covers a portion of the first surface that is not covered by the epitaxial structure and the first insulation layer, and has a light transmittance greater than that of the first insulation layer. An LED package, an LED module, and a display device including the LEDs are also disclosed.

Abstract: An integrated circuit includes a first active region, a first contact, a first gate, a first conductive line, a first conductor and a first via. In some embodiments, the first active region extends in a first direction. In some embodiments, the first contact extends in a second direction, and overlaps at least the first active region. In some embodiments, the first gate extends in the second direction, and overlaps the first active region. In some embodiments, the first conductive line extends in the first direction, and overlaps the first gate. In some embodiments, the first conductor overlaps the first contact, the first gate and the first conductive line, and extends in the first direction and the second direction. In some embodiments, the first via is between the first conductor and the first conductive line, and electrically couples the first conductor and the first conductive line together.