Abstract: A display apparatus and an image data processing method thereof are provided. The display apparatus includes a first display panel, a second display panel and a backlight module. The image processing method includes: receiving image data; detecting an ambient temperature and an ambient brightness to obtain a detection result; when the ambient temperature is lower than a preset temperature value, selecting the image data to be divided into a plurality block data by display location or gray level range according to the ambient brightness, and performing a blur process on the block data to generate adjusted image data; when the ambient temperature is not lower than the preset temperature value, performing a binary process on the image data to generate the adjusted image data; and driving the second display panel according to the adjust image data.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.

Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

Abstract: The present invention relates to a keyboard, including a base plate, a connecting element, a keycap, and a hook. The connecting element is separately connected to the hook and the base plate. The hook is disposed on an inner surface of the keycap and is connected to a connecting shaft of the connecting element. The hook includes a first fixing portion and a second fixing portion. The first fixing portion is in contact with a first side of the connecting shaft, and the second fixing portion is in contact with a second side of the connecting shaft. The structure of the second fixing portion in the hook is stronger than the structure of the first fixing portion, so that when the connecting shaft is applied with a force to be out of the hook, the first fixing portion is applied with an interference force to be broken, thereby having a recognizing effect.

Abstract: In example implementations, an antenna for a mobile device is provided. The antenna includes a printed circuit board and a plurality of metal members coupled to the printed circuit board. The printed circuit board is devoid of metal traces. The plurality of metal members is positioned along a length of the printed circuit board to operate at a desired frequency band when inserted into an opening along an outer edge perimeter of a metallic housing of the mobile device.

Abstract: A method for performing active noise control upon a target zone includes: using an adaptive filtering circuit to receive at least one microphone signal obtained from a microphone; and, dynamically compensating at least one coefficient of the adaptive filtering circuit to adjust a frequency response of the adaptive filtering circuit according to an energy distribution of the at least one microphone signal, so as to make the adaptive filtering circuit receive the at least one microphone signal to generate a resultant anti-noise signal to the target zone based on the dynamically adjusted frequency response.

Abstract: Certain donor plasmid vectors such as pFastBac™1 and pFastBac™ Dual lack a cis DNA element upstream of the polh translation start codon (ATG) present in wild type (wt) Autographa californica multiple nucleopolyhedrovirus (AcMNPV), and contain a SV40 pA fragment. When a cis DNA element is inserted upstream of the 50 bp polh promoter and SV40 pA was replaced with a AcMNPV polh pA signal in pFastBac™1 and pFastBac™Dual, certain protein expression levels in High Five™ cells using the Bac-to-Bac® system reached that of the wt AcMNPV.

Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.

Abstract: An electronic variable suspension system applicable to a motorcycle includes a plurality of sensors, a suspension unit, an actuation unit, and a control unit. The sensors are disposed in a front portion and/or rear portion of the motorcycle to sense acceleration, displacement, or frequency so as to generate a plurality of sensing signals. The suspension unit includes front and rear suspension devices disposed in the motorcycle. The actuation unit includes front and rear actuation devices coupled to the front suspension device and the rear suspension device, respectively. The control unit generates at least a control signal according to the sensing signals. The actuation unit changes a damping value and/or a preload value of the front suspension device and/or the rear suspension device according to the at least a control signal.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.

Abstract: A phase compensation method applied to a phase-locked loop (PLL) module of a communication device includes determining to output one of a maximum likelihood (ML) phase to an oscillator of the PLL module and a data-aided (DA) phase error to a filter of the PLL module according to an input signal. The ML phase is a phase generated from estimating known data in the input signal by using a ML method, and the DA phase error is a phase error generate from estimating the known data in the input signal by using a DA method.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.

Abstract: A method for forming a micro-electro mechanical system (MEMS) device is provided. The method includes bonding a semiconductor substrate with a carrier substrate through a dielectric layer and patterning the semiconductor substrate into multiple elements. The method also includes partially removing the dielectric layer to release some of the elements such that the released elements become one (or more) first movable element and one (or more) second movable element. The method further includes bonding a cap substrate with the semiconductor substrate to form a first closed chamber containing the first movable element and a second closed chamber containing the second movable element. In addition, the method includes opening the second closed chamber and sealing the second closed chamber after vacuumizing the second closed chamber such that the second closed chamber has a reduced pressure smaller than that of the first closed chamber.

Abstract: The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes dielectric layers and etch stop layers that are stacked in an alternating fashion. Metal wire layers are disposed within the stacked structure of the IMD region. The structure also includes a sensing electrode electrically connected to the IMD region with an electrode extension via. The structure includes a MEMS substrate comprising a MEMS device having a soft mechanical structure positioned adjacent to the sensing electrode.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: An echo cancellation circuit is provided to reduce or eliminate the effects of a pre-echo signal that is part of a received multi-path signal. The circuit includes: a delay module, receiving an input signal and delaying the input signal to generate a plurality of delayed signals; a multiplication module, multiplying the plurality of delayed signals by a plurality of coefficients to generate a plurality of multiplication results, respectively; a summing circuit, performing a summation on the plurality of multiplication results to generate a summation signal; a subtraction circuit, receiving a first delay signal and generating a subtracted signal according to the first delayed signal and the summation signal; and a coefficient calculating circuit, calculating the plurality of coefficients according to the subtracted signal. The echo cancellation circuit outputs an output signal as the subtracted signal, with the pre-echo signal diminished or eliminated.

Abstract: A semiconductor structure may include a first device having first surface with a first bonding layer formed thereon and a second device having a first surface with a second bonding layer formed thereon. The first bonding layer may provide an electrically conductive path to at least one electrical device in the first device. The second bonding layer may provide an electrically conductive path to at least one electrical device in the second device. One of the first or the second devices may include MEMS electrical devices. The first and/or the second bonding layers may be formed of a getter material, which may provide absorption for outgassing.

Abstract: A device includes a carrier having a plurality of cavities, a micro-electro-mechanical system (MEMS) substrate bonded on the carrier, wherein the MEMS substrate comprises a first side bonded on the carrier, a moving element over a bottom electrode, wherein the bottom electrode is formed of polysilicon and a second side having a plurality of bonding pads and a semiconductor substrate bonded on the MEMS substrate, wherein the semiconductor substrate comprises a top electrode and the first moving element is between the top electrode and the bottom electrode.