Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0?D1?D2 (but D1 and D2 are not zero at the same time).

Abstract: The present disclosure illustrates a bidirectional wireless charging device. The bidirectional wireless charging device comprises a transceiver chip which is configured to receive a switch signal. The transceiver chip comprises a power stage circuit and a control module. The power stage circuit is coupled to a coil, and the control module is coupled to the power stage circuit. The power stage circuit is configured to output a voltage to the coil, or to receive an induced voltage from the coil. The control module is configured to control the transceiver chip to enter a power mode or a charging mode based upon the switch signal. When the transceiver chip enters the power mode, the transceiver chip provides the voltage to the coil. When the transceiver chip enters the charging mode, the transceiver chip receives the induced voltage from the coil and charges a power storage unit.

Abstract: The present disclosure provides a device, such as a FET sensing cell, which includes a first dielectric layer over a substrate, an active layer over the first dielectric layer, a source region in the active layer, a drain region in the active layer, a channel region in the active layer situated between the source region and the drain region, a sensing film over the channel region, a second dielectric layer over the active layer, wherein an opening is formed in the second dielectric layer and the sensing film is located within the opening, a first electrode located within the second dielectric layer and a fluidic gate region located over the second dielectric layer and extending into the opening. The present disclosure also provides a method for improving the sensitivity of a device by adjusting a sensing value.

Abstract: The present disclosure relates to method of forming a MEMS device that mitigates the above mentioned difficulties. In some embodiments, the present disclosure relates to a method of forming a MEMS device, which forms one or more cavities within a first side of a carrier substrate. The first side of the carrier substrate is then bonded to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate, and the MEMS substrate is subsequently patterned to define a soft mechanical structure over the one or more cavities. The dielectric layer is then selectively removed, using a dry etching process, to release the one or more soft mechanical structures. A CMOS substrate is bonded to a second side of the MEMS substrate, by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate, using a low-temperature bonding process.

Abstract: Electroplating of aluminum may be utilized to form electrodes for solar cells. In contrast to expensive silver electrodes, aluminum allows for reduced cell cost and addresses the problem of material scarcity. In contrast to copper electrodes which typically require barrier layers, aluminum allows for simplified cell structures and fabrication steps. In the solar cells, point contacts may be utilized in the backside electrodes for increased efficiency. Solar cells formed in accordance with the present disclosure enable large-scale and cost-effective deployment of solar photovoltaic systems.

Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.

Abstract: A stacked semiconductor device includes a CMOS device and a MEMS device. The CMOS device includes a multilayer interconnect with metal elements disposed over the multilayer interconnect. The MEMS device includes metal sections with a first dielectric layer disposed over the metal sections. A cavity in the first dielectric layer exposes portions of the metal sections. A dielectric stop layer is disposed at least over the interior surface of the cavity. A movable structure is disposed over a front surface of the first dielectric layer and suspending over the cavity. The movable structure includes a second dielectric layer over the front surface of the first dielectric layer and suspending over the cavity, metal features over the second dielectric layer, and a flexible dielectric membrane over the metal features. The CMOS device is bonded to the MEMS device with the metal elements toward the flexible dielectric membrane.

Abstract: A dynamic flame simulating device mainly comprises an upper base, a flame element suspended from the upper base, a light source providing light rays, and a driving assembly below the flame element. The driving assembly further comprises an electromagnetic coil and a second magnetic element, wherein the electromagnetic coil is powered on to drive the second magnetic element to bounce toward a first magnetic element on the bottom end of the flame element to generate repellent magnetic acting forces to make the flame element swing naturally and achieve the dynamic visual effect of the natural beating of the burning flame.

Abstract: Various arrangements of color sub-pixels in a group of pixels for use in a color display are disclosed. The same group of pixels is repetitively arranged in rows and columns in the color display. In particular, each group of pixels has four pixels arranged on the four quadrants of a rectangle or square. A pixel group may have two sub-pixels in R, two sub-pixels in G, two sub-pixels in B and two sub-pixels in W, but each of the pixels has two different color sub-pixels. In each of the four pixels in a pixel group, the two sub-pixels can be adjacent to each other along the column direction or along the row direction, but the two sub-pixels in at least one pixel are adjacent to each other along the column direction. A pixel group may have two pixels with R, G sub-pixels and two pixels in B.

Abstract: The present invention relates to a patterned opto-electrical substrate, comprising a substrate, the substrate has a first patterned structure, a spacer region and a second patterned structure, wherein the second patterned structure is formed on one or both of the first patterned structure and the spacer region, and the first patterned structure is a micron-scale protruding structure or a micron-scale recessing structure, while the second patterned structure is a submicron-scale recessing structure. The present invention also relates to a method for manufacturing the aforementioned patterned opto-electrical substrate and light emitting diodes having the aforementioned patterned opto-electrical substrate.

Abstract: A method for forming thin film solar cell materials introducing a first inert gas mixture that includes hydrogen selenide into a chamber at a first pressure value until the chamber reaches a second pressure value and at a first temperature value, wherein the second pressure value is a predefined percentage of the first pressure value. The temperature in the chamber is increased to a second temperature value for a selenization process so that the pressure in the chamber increases to a third pressure value. Residual gas that is generated during the selenization process can be removed from the chamber. A second inert gas mixture that includes hydrogen sulfide is added into the chamber until the chamber reaches a fourth pressure value. The temperature in the chamber is increased to a third temperature value for a sulfurization process. The chamber is cooled after the sulfurization process.

Abstract: A microelectromechanical systems (MEMS) package includes a MEMS device and an integrated circuit (IC) device connected by a through silicon via (TSV). A conductive MEMS structure is arranged in a dielectric layer and includes a membrane region extending across a first volume arranged in the dielectric layer. A first substrate is bonded to a second substrate through the dielectric layer, where the MEMS device includes the second substrate. The TSV extends through the second substrate to electrically couple the MEMS device to the IC device. A third substrate is bonded to the second substrate to define a second volume between the second substrate and the third substrate, where the IC device includes the first or third substrate. A method for manufacturing the MEMS package is also provided.

Abstract: The present invention includes methods for the detection of neurotransmission or developmental disorders, including, but not limited to, myasthenia gravis that is seronegative for autoantibodies to the acetylcholine receptor (AChR) and/or muscle specific tyrosine kinase (MuSK), the method including detecting autoantibodies that bind to LRP4, or an epitope thereof. Also included are methods for the treatment of an individual suffering from a neurotransmission disorder, the method including detecting in a bodily fluid of the individual autoantibodies that bind to LRP4, or an epitope thereof, and administering to the patient an effective amount an immunosuppressant and/or another appropriate therapeutic modality. Also included are antibodies that bind to autoantibodies to LRP4 and kits for the detection of neurotransmission or developmental disorders.

Abstract: Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a plurality of stacked structures and a dielectric layer. The stacked structures are disposed on a substrate. The dielectric layer is disposed on the substrate, and covers the stacked structures. An air gap is located between two adjacent stacked structures, and a top end of the air gap is higher than a top end of each of the stacked structures.

Abstract: An apparatus for continuously forming a film through chemical vapor deposition includes a conveyor unit, a depositing unit and a cooling mechanism. The conveyor unit is for conveying a substrate along a moving path. The depositing unit includes at least one deposition chamber disposed to deposit a film-forming material on the substrate. The cooling mechanism includes inlet and outlet cooling units that are disposed oppositely relatively to the deposition chamber, that are communicated fluidly with the deposition chamber and that are controllable to provide a cooling temperature preventing the film-forming material from escaping and scattering away from the inlet and outlet cooling units.

Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.

Abstract: One method includes forming an anti-ferromagnetic layer on a substrate. A ferromagnetic layer may be formed on the anti-ferromagnetic layer. The ferromagnetic layer includes a first, second and third portions where the second portion is located between the first and third portions. A first ion irradiation is performed to only one portion of the ferromagnetic layer. A second ion irradiation is performed to another portion of the ferromagnetic layer.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.