Abstract: Disclosed are a feedblock multiplier with thickness gradient variation, a feedblock system, a method, and multilayer structure made by the method. The feedblock multiplier combines the functionalities of feedblock and multiplier conventionally used for producing the multilayer structure. The feedblock multiplier includes an input section for feeding fluid materials. A feedblock section is included for dividing the fluid delivered into multiple channels correspondingly. The fluids in the channels are segmented into two or more fluid segments by a segmenting section. The each fluid segment is delivered through corresponding channel-conversion section with thickness-gradient variation in the feedblock multiplier. Each channel-conversion section includes multiple channels with configurable positions. The fluids are then combined in a multiplier section for producing the multilayer structure with overlapped layers. The multilayer structure is outputted from an extruding section.

Abstract: The present disclosure relates to method of forming a MEMS device that mitigates the above mentioned difficulties. In some embodiments, the present disclosure relates to a method of forming a MEMS device, which forms one or more cavities within a first side of a carrier substrate. The first side of the carrier substrate is then bonded to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate, and the MEMS substrate is subsequently patterned to define a soft mechanical structure over the one or more cavities. The dielectric layer is then selectively removed, using a dry etching process, to release the one or more soft mechanical structures. A CMOS substrate is bonded to a second side of the MEMS substrate, by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate, using a low-temperature bonding process.

Abstract: The present disclosure is directed to a method of controlling network traffic for a user equipment (UE) and a base station (BS). In one of the exemplary embodiments, the disclosure is directed to a method of controlling network traffic for a UE. The method would include not limited to determining whether to select a target access network, and transmitting a traffic re-direct inform message in response to the selection of the target access network, wherein the traffic re-direct inform message comprises information of the target access network and a traffic flow indicator corresponding to at least one traffic flow.

Abstract: Methods and apparatuses for a magnetic tunnel junction (MTJ) which can be used in as a magnetic random access memory cell are disclosed. The MTJ comprises a free layer and an insulator layer. The MTJ further comprises a pinned layer with a first region, a second region, and a third region. The second region is of a first length and of a first thickness, and the first region and the third region are of a second length and of a second thickness. A ratio of the first thickness to the second thickness may be larger than 1.2. A ratio of the second length to the first length is larger than 0.5. The first thickness may be larger than a spin diffusion length of a material for the pinned layer. So formed MTJ results in increased tunneling magnetic resistance ratio and reduced critical switch current of the MTJ.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract: The present disclosure is directed to an apparatus and method for manufacture thereof. The apparatus includes a first passive substrate bonded to a second active substrate by a conductive metal interface. The conductive metal interface allows for integration of different function devices at a wafer level.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A recombinant baculovirus expression vector or cell comprising an engineered baculovirus fp25k gene with one to three modified or mutated spots, the modified spots comprise the two 7-adenine mononucleotide repeats (MNR) and the 10th TTAA site. The invention also provides the method of making the vector and baculovirus.

Abstract: A method for forming an integrated circuit device includes forming a dielectric layer onto a first substrate, forming a sacrificial material into a sacrificial cavity formed into the dielectric layer, forming a membrane layer over the dielectric layer and sacrificial material, releasing the sacrificial material through at least one via formed through the membrane layer, and bonding a capping substrate to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.

Abstract: A microelectromechanical systems (MEMS) package includes a MEMS device and an integrated circuit (IC) device connected by a through silicon via (TSV). A conductive MEMS structure is arranged in a dielectric layer and includes a membrane region extending across a first volume arranged in the dielectric layer. A first substrate is bonded to a second substrate through the dielectric layer, where the MEMS device includes the second substrate. The TSV extends through the second substrate to electrically couple the MEMS device to the IC device. A third substrate is bonded to the second substrate to define a second volume between the second substrate and the third substrate, where the IC device includes the first or third substrate. A method for manufacturing the MEMS package is also provided.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.

Abstract: A method for packaging a microelectromechanical system (MEMS) device with an integrated circuit die using wire bonds is provided. According to the method, a MEMS substrate having a MEMS device is provided. A cap substrate is secured to a top surface of the MEMS substrate. The cap substrate includes a recess corresponding to the MEMS device in a bottom surface of the cap substrate. An integrated circuit die is secured to a top surface of the cap substrate over the recess. A conductive stud or external wire bond electrically coupled with the integrated circuit die and extending vertically up is formed. A housing covering the MEMS substrate, the cap substrate, and the integrated circuit die, and with a top surface approximately coplanar with a top surface of the conductive stud or external wire bond, is formed. The structure resulting from application of the method is also provided.

Abstract: The present disclosure relates to a MEMS device with a magnetic film disposed on a first substrate, and an associated method of formation. In some embodiments, the magnetic film is disposed on a planar front surface of the first substrate such that depositing and patterning processes of the magnetic film is improved. A sensing gap of a MEMS device associated with the magnetic film is located between the magnetic film and a recessed lateral surface of a second substrate. The second substrate is bonded to the first substrate at front surfaces of the first and second substrate. Forming the magnetic film on the planar front allows for patterning of the magnetic film without leaving unwanted residues of magnetic material. Without the unwanted residue of magnetic material, less contamination from the magnetic material is introduced after dry etching and passivation processes, improving yield and reliability of the MEMS device.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: A displaying method includes following steps: converting first image data into second image data; performing subpixel rendering on second image data to generate third image data; determining whether the first image data includes first pixel data having a gray brightness value which is not greater than a first threshold; determining whether a gray brightness value of second pixel data of the third image data corresponding to the first pixel data is greater than a second threshold; and converting the third image data into fourth image data. The second pixel data is corresponding to third pixel data in the fourth image data. The third pixel data include at least one first subpixel data having a gray brightness value smaller than the gray brightness value of the subpixel data of the third image data corresponding to the first subpixel data.

Abstract: A method for forming an integrated semiconductor device includes providing a first wafer, providing a second wafer, and bonding the first wafer over the second wafer. The first wafer includes a first substrate having a microelectromechanical system (MEMS) device layer. The second wafer includes a second substrate having at least one active device, and at least one interconnect layer over the second substrate. The MEMS device layer is connected with the at least one interconnect layer. The method further includes forming at least one conductive plug through the first substrate and the MEMS device layer and inside the at least one interconnect layer, etching the second substrate and the at least one interconnect layer to form a cavity extending from a surface of the second substrate to the MEMS device layer, and etching the first substrate and the MEMS device layer to form a MEMS device interfacing with the cavity.

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.