Abstract: An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.

Abstract: A reagent is provided for removing mercury (Hg). The reagent contains metal carbonates compound with layers structure. The contents of metals of reagent can be adjusted using this method. The reagent can be manufactured with kilogram grade per batch. The common ions, like Mg, Ca, Mn, Fe, Co, Ni, Cu, Zn, etc., can be contained in the reagent. The manufacture method provides a low-cost way for the Hg sorbent and the content ratio of metal oxides can be higher than 50 wt %. The manufacture is operated at a temperature more than 200° C. and can be integrated with existing technology such as denitration catalysts in industry for removing Hg. In another word, the present invention fabricates a mercury-removing reagent of metal-M/aluminum carbonates (M-Al—CO3), which can be potentially combined with commercially selective catalytic reduction (SCR) catalysts for developing medium-high-temperature mercury-removing reagent with mercury-removing efficiency further enhanced.

Abstract: A semiconductor structure for a microelectromechanical systems (MEMS) device is provided. A first substrate region includes an electrical isolation layer arranged over a top surface of the first substrate region. A second substrate region is arranged over the electrical isolation layer and includes a MEMS device structure arranged within the second substrate region. The MEMS device structure includes a fixed mass and a proof mass. A dielectric region is arranged over the electrical isolation layer around the fixed mass. A fixed mass electrode is arranged around the dielectric region, and extends through the second substrate region to the electrical isolation layer. An isolated electrode extends through the second substrate region and the electrical isolation layer to the first substrate region on an opposite side of the proof mass as the fixed mass electrode. The method of forming the semiconductor structure is also provided.

Abstract: A fan module includes a casing, a fan, and two vibration absorption assemblies. The casing has an accommodating space. The fan is located in the accommodating space and keeps a distance from the casing. Each of the two vibration absorption assemblies includes two first vibration absorption components and a second vibration absorption component. The two first vibration absorption components are respectively in contact with the fan and separated from the casing, respectively. The second vibration absorption component is connected with two first vibration absorption components and the casing, respectively. The first vibration absorption components and the second vibration absorption components are adapted for absorbing the vibration waves having different frequency ranges.

Abstract: A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.

Abstract: The present invention includes methods for the detection of neurotransmission or developmental disorders, including, but not limited to, myasthenia gravis that is seronegative for autoantibodies to the acetylcholine receptor (AChR) and/or muscle specific tyrosine kinase (MuSK), the method including detecting autoantibodies that bind to LRP4, or an epitope thereof. Also included are methods for the treatment of an individual suffering from a neurotransmission disorder, the method including detecting in a bodily fluid of the individual autoantibodies that bind to LRP4, or an epitope thereof, and administering to the patient an effective amount an immunosuppressant and/or another appropriate therapeutic modality. Also included are antibodies that bind to autoantibodies to LRP4 and kits for the detection of neurotransmission or developmental disorders.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises one or more spring structures, such as a first spring structure and a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer, such as for CMOS outgassing relief. One or more thermal insulator structures are formed between the CMOS wafer and the MEMS wafer to protect the MEMS wafer from heat originating from the CMOS wafer.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

Abstract: A voltage detection circuit comprises a reference resistor including a terminal for receiving a first voltage; a reference transistor including a control terminal for receiving a second voltage; a comparator, including a first input terminal for receiving a converted voltage and a second input terminal for receiving the second voltage, for generating an output voltage; and a voltage dropping circuit series, comprising a plurality of voltage dropping circuits connected in a series, for converting an input voltage into the converted voltage; wherein the comparator indicates whether the input voltage matches a specific multiple of a voltage difference between the first voltage and the second voltage, and the specific multiple relates to a number of the plurality of voltage dropping circuits.

Abstract: A method for forming a MEMS device is provided. The method includes the following steps of providing a substrate having a first portion and a second portion; fabricating a membrane type sensor on the first portion of the substrate; and fabricating a bulk silicon sensor on the second portion of the substrate.

Abstract: A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.

Abstract: Disclosed are a feedblock multiplier with thickness gradient variation, a feedblock system, a method, and multilayer structure made by the method. The feedblock multiplier combines the functionalities of feedblock and multiplier conventionally used for producing the multilayer structure. The feedblock multiplier includes an input section for feeding fluid materials. A feedblock section is included for dividing the fluid delivered into multiple channels correspondingly. The fluids in the channels are segmented into two or more fluid segments by a segmenting section. The each fluid segment is delivered through corresponding channel-conversion section with thickness-gradient variation in the feedblock multiplier. Each channel-conversion section includes multiple channels with configurable positions. The fluids are then combined in a multiplier section for producing the multilayer structure with overlapped layers. The multilayer structure is outputted from an extruding section.

Abstract: There is provided a back side illuminated semiconductor structure with a semiconductor capacitor connected to a floating diffusion node in which the semiconductor capacitor for reducing a dimension of the floating diffusion node is provided above the floating diffusion node so as to eliminate the influence thereto by incident light and enhance the light absorption efficiency.

Abstract: Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: A semiconductor structure for a microelectromechanical systems (MEMS) device is provided. A first substrate region includes an electrical isolation layer arranged over a top surface of the first substrate region. A second substrate region is arranged over the electrical isolation layer and includes a MEMS device structure arranged within the second substrate region. The MEMS device structure includes a fixed mass and a proof mass. A dielectric region is arranged over the electrical isolation layer around the fixed mass. A fixed mass electrode is arranged around the dielectric region, and extends through the second substrate region to the electrical isolation layer. An isolated electrode extends through the second substrate region and the electrical isolation layer to the first substrate region on an opposite side of the proof mass as the fixed mass electrode. The method of forming the semiconductor structure is also provided.

Abstract: Chemical-mechanical polishing (CMP) compositions and methods are described, which are suitable for polishing an aluminum surface. The compositions comprise alumina abrasive particles coated with an anionic polymer, and suspended in an acidic or neutral pH carrier. In some cases, a polishing aid such as silica, a carboxylic acid, a phosphonic acid compound, or a combination thereof may be added to the CMP compositions. The described CMP compositions and methods improve polishing efficacy and reduce surface imperfections on a polished aluminum surface compared to CMP methods using uncoated alumina abrasive.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain, A TFT is also provided.

Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Abstract: An electronic device includes a receiver and an activator. The receiver includes a microphone; and a signal detector, coupled to the microphone, for determining whether a valid input signal received from the microphone is a voice signal or an ultrasonic signal by comparing a frequency of the valid input signal with at least two frequency bands, and accordingly passing the valid input signal. The activator includes a voice detection module, for performing a voice activated process; and an ultrasonic detection module, for performing an ultrasound activated process. The voice detection module and the ultrasonic detection module are enabled by the signal detector simultaneously or separately.