Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises a first spring structure and the MEMS wafer comprises a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer as a thermal insulation air gap to protect the MEMS wafer from heat originating from the CMOS wafer. The ambient pressure chamber is connected to ambient air, such as for CMOS outgassing relief.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The MEMS wafer comprises a thermal insulator air gap formed between a sensing layer and a membrane. An ambient pressure chamber is formed between the CMOS wafer and the membrane of the MEMS wafer. The ambient pressure chamber is configured as a second thermal insulator air gap. The thermal insulator air gap and the second thermal insulator air gap protect portions of the semiconductor arrangement, such as the MEMS wafer, from heat originating from the CMOS wafer, which can otherwise damage such portions of the semiconductor arrangement. In some embodiments, one or more buffer layers are formed over the cap wafer as stress buffers.

Abstract: A signal processing apparatus includes an initial detecting module, a mixer, a symbol rate detecting module, a judging module and a correcting module. The initial detecting module determines an initial carrier frequency offset of an input signal according to a spectrum of the input signal. The mixer adjusts the input signal according to the initial carrier frequency offset to generate a frequency-compensated signal. The symbol rate detecting module determines a symbol rate of the input signal. The judging module judges whether the initial carrier frequency offset is correct according to the frequency-compensated signal. When a judgment result of the judging module is negative, the correcting module determines a corrected carrier frequency offset according to the symbol rate and the spectrum.

Abstract: A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment.

Abstract: A stacked semiconductor device includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. The cavity has an interior surface. A stop layer is disposed over the interior surface of the cavity. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.

Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.

Abstract: A watermark and a manufacturing method therefor are provided. The watermark has a first region comprising amplitude modulation (AM) halftone dots and a second region comprising frequency modulation (FM) halftone dots, and each of the amplitude modulation halftone dots has ink portions and blank portions, each of which is located between the two ink portions in the same amplitude modulation halftone dot. The ink area percentage of the amplitude modulation halftone dots are dispersed by filling the blank portions into each of the amplitude modulation halftone dots, so that the density calibration of the amplitude modulation halftone dots and frequency modulation halftone dots can be omitted.

Abstract: The present disclosure relates to an integrated chip having a titanium nitride film that provides for a reduced leakage path, and an associated method of formation. In some embodiments, the integrated chip comprises a semiconductor substrate. A titanium nitride film is disposed over the semiconductor substrate. The titanium nitride film comprises a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride. The grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film. The discontinuity of the grain boundaries between the different titanium nitride layers reduces leakage paths through the titanium nitride film (e.g., and thereby can improve operation of a MIM capacitor having titanium nitride electrodes).

Abstract: A cooling fan includes a hub and an impeller. The hub includes a circular wall and an annular wall. The annular wall has a position end opposite to the circular wall. The impeller includes a blade ring and a plurality of blades integrally extending outwards from an outer circumferential surface of the blade ring. The blade ring receives the hub and has a first mounting end and a second mounting end opposite to the first mounting end. When the position end abuts the second mounting end of the blade ring, the blades extend aslant from the blade ring toward a counterclockwise direction relative to the circular wall. When the position end abuts the first mounting end of the blade ring, the blades extend aslant from the blade ring toward a clockwise direction relative to the circular wall.

Abstract: An exemplary housing of a cooling fan includes a metallic base plate and a plastic bear seat. Clasps extend upwardly from the base plate. The bear seat is formed on the base plate via injection process. A bottom end of the bear seat directly contacts the base plate. The clasps are embedded in the bear seat.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises a first spring structure and the MEMS wafer comprises a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer as a thermal insulation air gap to protect the MEMS wafer from heat originating from the CMOS wafer. The ambient pressure chamber is connected to ambient air, such as for CMOS outgassing relief.

Abstract: A hand puller with a rope reel contains a body and a reel. The body includes a fixing holder, a first rotary shaft, a rotating handle, two ratchet wheels, and at least one stopping piece. The rotating handle having a pushing plate, and the first rotary shaft has two driving gears. The reel includes a seat, a second rotary shaft, two driven gears, and a chain roller. The body includes a first connecting portion with plural holes, and the seat has a second connecting portion and a plurality of apertures. The reel and the body are movably coupled together, and the second connecting portion of the reel is aligned and overlapped with the first connecting portion of the body. At least one pin is inserted into at least one of the plural holes of the first connecting portion and the plurality of apertures of the second connecting portion.

Abstract: A driving method for rendering subpixels of each pixel of a display is provided. The display has a plurality of first pixels and a plurality of second pixels. Each second pixel has a first color subpixel and a second color subpixel, but lacks a third color subpixel. Each first pixel has a second color subpixel and a third color subpixel, but lacks a first color subpixel. The first color subpixel, second color subpixel and third color subpixel are used to represent gray levels of a first color, a second color and a third color respectively. Processes of rendering the subpixels of each pixel are performed based on positions, saturations and brightness of neighboring pixels, such that quality of image displayed on the display could be ensured even though each first pixel lacks the first color subpixel and each second pixel lacks the third color subpixel.

Abstract: A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates.

Abstract: A method of compensating the color gamut of a display includes establishing a plurality of color gamut boundaries of four color hues, generating m sets of original luminance, chrominance and hue values according to m sets of tricolor grey level values, adjusting the chrominance of n sets of luminance, chrominance and hue values of the m sets of luminance, chrominance and hue values exceeding the plurality of color gamut boundaries with four color hues to generate n sets of corrected luminance, chrominance and hue values, generating m sets of four color grey levels according to the n sets of corrected luminance, chrominance and hue values and (m?n) sets of uncorrected luminance, chrominance and hue values, and displaying images on the display according to the m sets of four color grey levels.

Abstract: An electroluminescence device comprises a sandwich structure and a first luminous unit. The sandwich structure comprises a first metal layer, an insulation layer, and a second metal layer stacked in sequence along a stacking direction. The first luminous unit is disposed on a sidewall of the sandwich structure parallel to the stacking direction, wherein the first luminous unit comprises a first electrode and a second electrode connected to the first metal layer and the second metal layer by a solder ball respectively.

Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.