Abstract: Methods for treating a wound or promote wound healing are provided, comprising the step of administering a composition including an effective amount of ?-1 adrenergic receptor antagonist to a subject in need thereof. Also provided is apparatus for wound healing, comprising a dressing and a composition including an effective amount of ?-1 adrenergic receptor antagonist.

Abstract: A quantum device includes a qubit chip having a plurality of qubits and an interposer attached to and electrically connected to the qubit chip. The device also includes a substrate handler attached to one side of the qubit chip or to one side of the interposer, or both so as to be thermally in contact with the qubit chip or the interposer, or both. The substrate handler includes a plurality of vias, at least a portion of plurality of vias being filled with a non-superconducting material, the non-superconducting material being selected to dissipate heat generated in the qubit chip, the interposer or both.

Abstract: A wiring structure and a method for manufacturing a wiring structure are provided. The wiring structure includes a first conductive structure, a second conductive structure, a dent structure and an adhesion layer. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The dent structure is attached to the first conductive structure. The adhesion layer is interposed between the first conductive structure and the second conductive structure to bond the first conductive structure and the second conductive structure together. A periphery portion of the adhesion layer is disposed in a gap between the dent structure and the second conductive structure.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A wiring structure and a method for manufacturing a wiring structure are provided. The wiring structure includes a first conductive structure, a second conductive structure, a dent structure and an adhesion layer. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The dent structure is attached to the first conductive structure. The adhesion layer is interposed between the first conductive structure and the second conductive structure to bond the first conductive structure and the second conductive structure together. A periphery portion of the adhesion layer is disposed in a gap between the dent structure and the second conductive structure.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. Each of the sub-layers is formed from a polymeric material. A boundary is formed between two adjacent sub-layers.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A socket is provided, including a first member, a second member and a third member. The second member is movably inserted within the first member. The third member is movably sleeved with the first member.

Abstract: A drug delivery form includes a drug and electronics. The electronics includes memory(ies) having drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The electronics includes communication circuitry configured to read data from and write data to the drug delivery form information. An apparatus includes memory(ies) having computer readable code, and processor(s). The processor(s) cause the apparatus to perform operations including communicating with a drug delivery form including a drug and drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The processor(s) cause the apparatus to perform reading data from or writing data into the drug and drug delivery form information.

Abstract: A light-emitting element includes a semiconductor light-emitting stack including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween; a first conductive layer disposed on the second semiconductor layer and electrically connecting the second semiconductor layer; a second conductive layer disposed on the second semiconductor layer and electrically connecting the first semiconductor layer; and a cushion part disposed on and directly contacts the first conductive layer, wherein in a top view, the cushion part is surrounded by and electrically isolated from the second conductive layer.

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: A semiconductor wafer cleaning apparatus is provided. The semiconductor wafer cleaning apparatus includes a spin base, a spindle, a clamping member, and a first sealing ring. The spin base has a through hole and a flange. The spindle extends through the through hole. The clamping member covers the through hole and is connected to the spindle. The clamping member includes a mounting part. The first sealing ring is disposed under the clamping member. A top surface of the first sealing ring and a top surface of the flange are in contact with a bottom surface of the mounting part.