Patents by Inventor Wen Hung (Steven) Lu

Wen Hung (Steven) Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020832
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Publication number: 20210013163
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
  • Patent number: 10892213
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Li-Yu Hsieh, Yan Wen Chung
  • Patent number: 10890979
    Abstract: A controlling system and a controlling method for virtual display are provided. The controlling system for virtual display includes a visual line tracking unit, a space forming unit, a hand information capturing unit, a transforming unit and a controlling unit. The visual line tracking unit is used for tracking a visual line of a user. The space forming unit is used for forming a virtual display space according to the visual line. The hand information capturing unit is used for obtaining a hand location of the user's one hand in a real operation space. The transforming unit is used for transforming the hand location to be a cursor location in the virtual display space. The controlling unit is used for controlling the virtual display according to the cursor location.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 12, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Duan-Li Liao, Chia-Chang Li, Wen-Hung Ting, Hian-Kun Tenn
  • Patent number: 10883142
    Abstract: A method of predicting the risk of a patient for developing phenytoin-induced adverse drug reactions (ADRs), including Stevens-Johnson syndrome (SJS), toxic epidermal necrolysis (TEN), or drug reactions with eosinophilia and systemic symptoms (DRESS) is disclosed. Genetic polymorphisms of CYP2C genes (including rs1057910 (CYP2C9*3) and rs3758581 on CYP2C19), and HLA alleles (including HLA-B*1502, HLA-B*1301, and HLA-B*5101) can predict adverse reactions caused by phenytoin or fosphenytoin. Accordingly, the present invention provides a kit to assess the risk of a patient for developing adverse reactions in response to phenytoin-related drugs, which comprises the determination of the presence of a specific allele selected from the group consisting of rs1057910 (CYP2C9*3), rs3758581 on CYP2C19, HLA-B*1502, HLA-B*1301, and HLA-B*5101, wherein the presence of at least one allele is indicative of a risk for the adverse drug reactions.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 5, 2021
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, National Yang-Ming University
    Inventors: Wen-Hung Chung, Shuen-Iu Hung
  • Publication number: 20200413448
    Abstract: A communications apparatus includes a plurality of communications circuits and a coexistence management circuit. Each communications circuit is configured to provide wireless communications services in compliance with a protocol. The coexistence management circuit is configured to manage radio activities of the communications circuits. In response to a detection result of at least two radio activities to occur in a subsequent packet time, the coexistence management circuit is configured to determine whether an interference signal related to said at least two radio activities falls in a predetermined frequency band, and when the interference signal falls in the predetermined frequency band, the coexistence management circuit is configured to adjust a transmission power or an execution time of one of said at least two radio activities.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 31, 2020
    Inventors: Yu-Ming Lai, Kai-Hsiang Yang, Wen-Ying Chien, Tsai-Yuan Hsu, Yu-Hsien Chang, Yu-Ming Wen, Ying-Che Hung, Pei-Wen Hung
  • Publication number: 20200411402
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Patent number: 10878916
    Abstract: An erasing method adapted for a semiconductor memory device is provided. The erasing method includes executing a pre-program process on the semiconductor memory device, executing an erase process on the semiconductor memory device, executing an over-erase verification process on a plurality of memory cells of the semiconductor memory device, detecting a total current consumption of the plurality of memory cells, determining the number of the memory cells to be executed with a soft program process according to the total current consumption, and executing the soft program process on the memory cells based on the number of the memory cells.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Kai Liao, Chiang-Hung Chen, Wen Hung
  • Publication number: 20200404402
    Abstract: A speaker includes a sound box, a speaker module, and a heat pipe. The sound box includes a first opening and a second opening. The speaker module is hermetically connected to the first opening. The heat pipe is hermetically connected to the second opening. The heat pipe includes a first end and a second end. The first end is located in the sound box. The second end is exposed to the second opening. The speaker module is fixedly connected to at least part of an outer wall of the heat pipe. In the speaker, a hollow heat pipe is fixedly connected to the speaker module, and vibration of the speaker module drives air in the heat pipe to flow to dissipate heat from the heat pipe. Further, the cold heat pipe carries heat away from the speaker module through heat transfer, thereby dissipating heat from the speaker.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 24, 2020
    Inventor: Wen-Hung LIN
  • Publication number: 20200400917
    Abstract: A lens assembly driving module includes a holder, a metal yoke, a lens unit, a magnet set, a coil, at least one elastic element and at least one damper agent. The metal yoke is coupled with the holder and includes a through hole and at least one extending structure. The extending structure is disposed around the through hole and extends along a direction from the through hole to the holder. The lens unit is movably disposed in the metal yoke. The lens unit includes an optical axis and at least one notch structure. The notch structure is disposed in an outer peripheral area of the lens unit and is corresponding to the extending structure. The damper agent is disposed between the extending structure of the metal yoke and the notch structure of the lens unit. The damper agent is applied to damp a movement of the lens unit.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Yi LU, Te-Sheng TSENG, Wen-Hung HSU, Ming-Ta CHOU
  • Publication number: 20200395115
    Abstract: A drug delivery form includes a drug and electronics. The electronics includes memory(ies) having drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The electronics includes communication circuitry configured to read data from and write data to the drug delivery form information. An apparatus includes memory(ies) having computer readable code, and processor(s). The processor(s) cause the apparatus to perform operations including communicating with a drug delivery form including a drug and drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The processor(s) cause the apparatus to perform reading data from or writing data into the drug and drug delivery form information.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: John Knickerbocker, Li-Wen Hung, Bing Dang, Katsuyuki Sakuma, Jeffrey Donald Gelorme, Rajeev Narayanan, Qianwen Chen
  • Patent number: 10866658
    Abstract: An indicator device is suitable for a mixed reality device. The indicator device includes a body, a light source unit, at least two positioning elements, a triggering unit and a control unit. The light source unit is disposed on the body and generates a light source. The two elements are disposed separately on the body, wherein the light source unit and the positioning elements are disposed on different axes. The triggering unit is disposed on the body and generates a trigger signal. The control unit is disposed inside the body and is connected to the light source unit and the triggering unit. The control unit receives the trigger signal to generate a first control signal, thereby controlling the light-emitting state of the light source.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 15, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Bin Luo, Chun-Chuan Lin, Wen-Hung Cheng, Ming-Che Wang
  • Publication number: 20200388600
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
  • Publication number: 20200386969
    Abstract: A lens driving apparatus is for driving a lens assembly and includes a base, a metal cover, a carrier, a first coil, at least one first magnet, at least one second magnet, a frame and a spring set. At least one lower leaf spring of the spring set includes a frame connecting section, a carrier connecting section and a resilient section. The carrier connecting section and the second magnet are arranged along the first direction. The carrier connecting section includes an opening portion and a shielding portion, and the opening portion and the shielding portion both corresponding to the second magnet along the first direction are respectively for a part of the second magnet to be exposed through the opening portion and another part of the second magnet to be shielded by the shielding portion.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Te-Sheng TSENG, Wen-Hung HSU, Yung-Chun KANG
  • Patent number: 10861780
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Publication number: 20200381375
    Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG, Yuh-Shan SU
  • Publication number: 20200381369
    Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Huei-Shyong CHO
  • Patent number: 10854624
    Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Wen Hung, Yu-Kai Liao, Chiang-Hung Chen
  • Publication number: 20200368880
    Abstract: A socket includes a first and a second sleeve members. The first sleeve member has a first end for connecting to a driving tool and a second end having a first connecting portion for sleeving onto a first fastener, and has an internal space and an internal circumferential wall. The second sleeve member is movably inserted into the internal space and has an external circumferential wall and a second connecting portion connected together. The second connecting portion is for sleeving onto a second fastener whose size is different from a size of the first fastener. One of the external and the internal circumferential walls is tapered from the first end toward the second end to form a gap. The other one of the external and the internal circumferential walls has a restriction unit extending into the gap.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Inventor: WEN-HUNG CHIANG
  • Patent number: D906286
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Bose Corporation
    Inventor: Wei Wen Hung