Patents by Inventor Wen Hung (Steven) Lu

Wen Hung (Steven) Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200374895
    Abstract: The present invention provides a wireless communication method of a wireless device, wherein the wireless device includes a first wireless module and a second wireless module, and the wireless communication method includes the steps of: using the first wireless module to receive frame exchange information from the second wireless module, wherein the frame exchange information comprises timing of signal transmission and signal reception of the second wireless module; and scheduling signal transmission and signal reception of the first wireless module according to the frame exchange information of the second wireless module.
    Type: Application
    Filed: May 6, 2020
    Publication date: November 26, 2020
    Inventors: Tsai-Yuan Hsu, Pei-Wen Hung
  • Publication number: 20200373334
    Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee Wee Liu
  • Publication number: 20200365500
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 19, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Patent number: 10835156
    Abstract: A thermal tag for activity monitoring. The thermal tag includes a base layer having a plurality of metal lines to provide a conductive path, and a pattern layer having one or more infrared emitting features positioned over portions of the conductive path, wherein at least one infrared emitting feature couples to the conductive path to emit a predetermined infrared pattern in accordance with nearby activity.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Wen Hung, Jui-Hsin Lai
  • Patent number: 10840437
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: November 17, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Publication number: 20200357956
    Abstract: A semiconductor light-emitting device includes a substrate; a first semiconductor layer and a second semiconductor layer formed on the substrate, wherein the first semiconductor layer includes a first exposed portion and a second portion; a plurality of first trenches formed on the substrate and including a surface composed by the first exposed portion; a second trench formed on the substrate and including a surface composed by the second exposed portion at a periphery region of the semiconductor light-emitting device, wherein each of the plurality of first trenches is branched from the second trench; and a patterned metal layer formed on the second semiconductor layer and including a first metal region and a second metal region, and portions of the second metal region are formed in the plurality of first trenches and the second trench to electrically connect to the first exposed portion and the second exposed portion.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Tsung-Hsun CHIANG, Bo-Jiun HU, Wen-Hung CHUANG, Yu-Ling LIN
  • Publication number: 20200355385
    Abstract: An air conditioning device is provided. The air conditioning device includes a power supplier, a compressor driver, a fan driver, a temperature sensor, a vibration sensor, and an operation processing controller. The power supplier has an input end receiving an input power source and generates a first operating power source and a second operating power source according to the input power source. The compressor driver operates according to the first operating power source to generate a first drive signal to drive a compressor. The fan driver operates according to the first operating power source to generate a second drive signal to drive a fan. The vibration sensor detects vibration information of the air conditioning device.
    Type: Application
    Filed: March 16, 2020
    Publication date: November 12, 2020
    Applicant: Chizentek Inc.
    Inventors: Chih-Chuan Liang, Wen-Hung Lo
  • Patent number: 10833048
    Abstract: A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Wen Hung, Reinaldo Vega, Hari Mallela
  • Publication number: 20200350254
    Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20200350240
    Abstract: A wiring structure includes at least one upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer, at least one upper circuit layer in contact with the upper dielectric layer, and at least one bonding portion electrically connected to the upper circuit layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20200341350
    Abstract: A camera driving module includes: a base including a central opening; a casing disposed on the base and including an opening hole corresponding to the central opening; a lens unit movably disposed on the casing; and a focus driving part. The focus driving part includes a carrier, an AF coil element, at least two permanent magnets and a Hall element. The carrier is disposed on the lens unit and movable in a direction parallel to an optical axis. The AF coil element is fixed to the base and faces toward the carrier. The permanent magnets are fixed on one side of the carrier facing toward the base and disposed opposite to each other about the optical axis. The Hall element faces toward a corresponding surface of one of the permanent magnets. The AF coil element and the corresponding surfaces are arranged in the direction parallel to the optical axis.
    Type: Application
    Filed: November 18, 2019
    Publication date: October 29, 2020
    Applicant: LARGAN DIGITAL CO.,LTD.
    Inventors: Te-Sheng TSENG, Ming-Ta CHOU, Wen-Hung HSU
  • Publication number: 20200343212
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20200335961
    Abstract: A hot-swap circuit for providing soft start and overcurrent protection to an electronic circuit may include a controller and a timer. The controller may be configured to sense an electrical current associated with the hot-swap circuit, based on the electrical current sensed, perform current limiting of the electrical current to minimize inrush current to the electronic circuit, and disable the electrical current from flowing to the electronic circuit in response to the electrical current exceeding an overcurrent threshold for longer than a duration of a fault timer. The timer circuit may be configured to, for a period of time after enabling of the hot-swap circuit, cause the duration of the fault timer to be a first duration, and after the period of time, cause the duration of the fault timer to be a second duration significantly shorter than the first duration.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: Dell Products L.P.
    Inventors: Wen-Hung HUANG, Kunrong WANG, Hsien Tsung LIN
  • Patent number: 10811305
    Abstract: A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Li-Wen Hung, John U. Knickerbocker, Leathen Shi, Cornelia Tsang Yang, Bucknell C. Webb
  • Patent number: 10811413
    Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Reinaldo Vega, Choonghyun Lee, Hari Mallela, Li-Wen Hung
  • Patent number: 10802243
    Abstract: A lens assembly driving module includes a holder, a metal yoke, a lens unit, a magnet set, a coil, at least one elastic element and at least one damper agent. The metal yoke is coupled with the holder and includes a through hole and at least one extending structure. The extending structure is disposed around the through hole and extends along a direction from the through hole to the holder. The lens unit is movably disposed in the metal yoke. The lens unit includes an optical axis and at least one notch structure. The notch structure is disposed in an outer peripheral area of the lens unit and is corresponding to the extending structure. The damper agent is disposed between the extending structure of the metal yoke and the notch structure of the lens unit. The damper agent is applied to damp a movement of the lens unit.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 13, 2020
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Chun-Yi Lu, Te-Sheng Tseng, Wen-Hung Hsu, Ming-Ta Chou
  • Patent number: 10805510
    Abstract: A camera driving module includes a base, a casing, a lens unit, a magnetic element, a coil, a spring and a damper agent. The base includes an opening. The casing is disposed on the base and includes a through hole and a broadwise notch structure. The broadwise notch structure is located nearby a periphery of the through hole. The lens unit is movably disposed on the casing and includes a protruding structure. The protruding structure is located at a periphery of the lens unit. The magnetic element is fixed to the casing and located at an inside the casing. The coil is fixed to the lens unit and located at an outside of the lens unit. The coil faces toward the magnetic element. The spring is disposed on the lens unit. The damper agent is disposed between the broadwise notch structure and the protruding structure.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: October 13, 2020
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Te-Sheng Tseng, Ming-Ta Chou, Wen-Hung Hsu
  • Publication number: 20200318189
    Abstract: A method for assessing the risk of cutaneous adverse drug reactions induced by an anti-epileptic drug Lamotrigine is provided, wherein the cutaneous adverse drug reactions include but are not limited to: maculopapular eruption (MPE), fixed drug eruption (FDE), Stevens Johnson Syndrome (SJS), toxic epidermal necrolysis (TEN), drug rash with eosinophilia and systemic symptoms (DRESS). Further provided is a detection reagent for assessing the risk of a patient developing the cutaneous adverse drug reactions induced by the anti-epileptic drug Lamotrigine, comprising agents for measuring a particular HLA allele and the use thereof.
    Type: Application
    Filed: October 27, 2017
    Publication date: October 8, 2020
    Inventors: Shuen-Iu HUNG, Wen-Hung CHUNG
  • Patent number: 10796928
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Publication number: 20200312912
    Abstract: A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: REINALDO VEGA, TAKASHI ANDO, HARI MALLELA, Li-Wen Hung