Patents by Inventor Wen Hung (Steven) Lu

Wen Hung (Steven) Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10520019
    Abstract: A slide module comprises an outer rail, a ball rail, first balls and second balls. The outer rail has a first inner surface and a second inner surface. The ball rail has a first holding section and a second holding section. The first balls are rollably disposed in a plurality of first holes of the first holding section in which the first ball is contacted with the first inner surface and the second holding section and distant from the second inner surface. The second balls are rollably disposed in a plurality of second holes of the second holding section in which the second ball is contacted with the second inner surface and the first holding section and distant from the inner surface. Thereby, the ball rail is capable of moving along the axial direction with respect to the outer rail through the first balls and the second balls.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: December 31, 2019
    Assignee: SYNCMOLD ENTERPRISE CORP.
    Inventors: Wen-Hung Lo, Kuang-Yao Wu, Ching-Hui Yen
  • Patent number: 10510884
    Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate is formed on a semiconductor substrate. The dummy gate has a first sidewall and a second sidewall opposite to the first sidewall. A low-k dielectric layer is formed on the first sidewall of the dummy gate and the semiconductor substrate. A spacer material layer is deposited on the low-k dielectric layer, the second sidewall of the dummy gate, and the semiconductor substrate. The spacer material layer and the low-k dielectric layer are etched to form a first spacer structure on the first sidewall and a second spacer structure on the second sidewall. A drain doping region is formed in the semiconductor substrate adjacent to the first spacer structure. A source doping region is formed in the semiconductor substrate adjacent to the second spacer structure.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chun-Hsien Lin
  • Patent number: 10508022
    Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 17, 2019
    Assignee: INVENSENSE, INC.
    Inventors: Michael J. Daneman, Martin Lim, Xiang Li, Li-Wen Hung
  • Publication number: 20190378719
    Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.
    Type: Application
    Filed: August 25, 2019
    Publication date: December 12, 2019
    Inventors: Russell A. Budd, Qianwen Chen, Bing Dang, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker
  • Publication number: 20190378720
    Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.
    Type: Application
    Filed: August 26, 2019
    Publication date: December 12, 2019
    Inventors: Russell A. Budd, Qianwen Chen, Bing Dang, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker
  • Patent number: 10504605
    Abstract: A method for testing firmware of an SSD includes: controlling a main memory to emulate volatile and non-volatile memories of the SSD, fetching a testing sequence and a testing criterion, fetching read/write operations from binary codes generated by compiling the firmware, determining whether the read/write operations are associated with a marker, executing the read/write operations when a result of determination is affirmative, otherwise discarding a read/write of data, monitoring whether processes of executing of the read/write operations meet the testing criterion, and generating a result of a test of the firmware when it is monitored that the testing criterion is met.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: December 10, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung
  • Patent number: 10505160
    Abstract: A pre-cut glass body is employed as a separator between an anode current collector and a cathode current collector of a micro-battery. The use of a pre-cut glass body in micro-battery applications provides excellent insulation for the micro-battery and can also result in enhanced battery reliability and lifetime.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Qianwen Chen, Yang Liu, Li-Wen Hung
  • Patent number: 10495945
    Abstract: A dual lens driving apparatus includes a holder, a metal yoke, a carrier, a first coil, at least one magnet and at least one first sensing component. The carrier is movably disposed in the metal yoke, wherein the carrier includes a first receiving space and a second receiving space, the first receiving space and the second receiving space are for receiving a first lens assembly and a second lens assembly respectively, a central axis of the first receiving space and a central axis of the second receiving space are parallel, the carrier can be moved at least along a first direction, and the first direction is parallel to the two central axes. The magnet is movably disposed in the metal yoke, wherein the magnet can be moved at least along a second direction, and the second direction is vertical to the two central axes.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 3, 2019
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Te-Sheng Tseng, Wen-Hung Hsu, Yung-Chun Kang
  • Publication number: 20190364181
    Abstract: A camera driving module includes a base, a casing, a lens unit, a magnetic element, a coil, a spring and a damper agent. The base includes an opening. The casing is disposed on the base and includes a through hole and a broadwise notch structure. The broadwise notch structure is located nearby a periphery of the through hole. The lens unit is movably disposed on the casing and includes a protruding structure. The protruding structure is located at a periphery of the lens unit. The magnetic element is fixed to the casing and located at an inside the casing. The coil is fixed to the lens unit and located at an outside of the lens unit. The coil faces toward the magnetic element. The spring is disposed on the lens unit. The damper agent is disposed between the broadwise notch structure and the protruding structure.
    Type: Application
    Filed: August 13, 2019
    Publication date: November 28, 2019
    Applicant: LARGAN DIGITAL CO.,LTD.
    Inventors: Te-Sheng TSENG, Ming-Ta CHOU, Wen-Hung HSU
  • Patent number: 10490525
    Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qianwen Chen, Bing Dang, Russell Budd, Bo Wen, Li-Wen Hung, Jae-Woong Nah, John Knickerbocker
  • Patent number: 10483215
    Abstract: A multi-layer wafer and method of manufacturing such wafer are provided. The method includes applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Gelorme, Li-Wen Hung, John U. Knickerbocker
  • Publication number: 20190348352
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Chien-Mei HUANG, Yan Wen CHUNG
  • Publication number: 20190348392
    Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: Qianwen Chen, Bing Dang, Russell Budd, Bo Wen, Li-Wen Hung, Jae-Woong Nah, John Knickerbocker
  • Publication number: 20190348570
    Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer; a plurality of first trenches penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer; a second trench penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the active layer and the plurality of first trenches; a patterned metal layer formed on the second semiconductor layer and formed in one of the plurality of first trenches or the second trench; and a first pad portion and a second pad portion both formed on the second semiconductor layer and electrically connecting the second semiconductor layer and the first semiconductor layer respectively.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Tsung-Hsun CHIANG, Bo-Jiun HU, Wen-Hung CHUANG, Yu-Ling LIN
  • Patent number: 10474893
    Abstract: An electronic device, an iris recognition method and a non-volatile computer-readable medium are provided. A processor in the electronic device obtains a first and second iris images, and calculates a plurality of first and second feature mark boxes that are non-uniformly arranged according to the first and second iris images. The processor uses the first feature mark boxes to obtain a first and second image features from the first and second iris images respectively, and compares the first and second image features to obtain a first recognition result. The processor uses the second feature mark boxes to obtain a third and fourth image features from the second and first iris images respectively, and compares the third and fourth image features to obtain a second recognition result. The processor determines a similarity degree of the first and second iris images according to the first and second recognition results.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 12, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Hung Ting, Hian-Kun Tenn, Duan-Li Liao, Chia-Chang Li, Po-Lung Chen
  • Publication number: 20190339482
    Abstract: A lens driving apparatus includes a holder, a metal cover, a carrier, a sensing magnet, a printed circuit board, a position sensor, a coil and at least one driving magnet. The metal cover is coupled with the holder and has an opening. The carrier is assembled to a lens assembly having an optical axis, wherein the carrier is disposed in the metal cover and is movable along a direction parallel to the optical axis. The sensing magnet is coupled with the carrier. The printed circuit board is disposed near to one of the four lateral sides of the holder. The position sensor is disposed on the printed circuit board and corresponds to the sensing magnet. The coil is disposed on an outer surface of the carrier. One of the driving magnet is disposed in the metal cover and corresponds to the coil.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Te-Sheng TSENG, Wen-Hung HSU, Ming-Ta CHOU
  • Publication number: 20190339480
    Abstract: A lens assembly actuating module includes a holder, a metal yoke, a lens actuator and a Hall sensor. The holder includes a central opening, at least three metal connectors insert-molded with the holder, at least two metal terminals insert-molded with the holder, and a plurality of plated metal layers disposed on a surface of the holder. The metal yoke is coupled with the holder. The lens actuator is for carrying a lens unit including an optical axis. The lens actuator is movably disposed in the metal yoke. The lens actuator includes at least one elastic element and at least three metal hanging wires. The Hall sensor is disposed on one of the plated metal layers of the holder. The Hall sensor is for detecting a movement of the lens unit along a direction perpendicular to the optical axis.
    Type: Application
    Filed: December 14, 2018
    Publication date: November 7, 2019
    Inventors: Te-Sheng TSENG, Wen-Hung HSU, Ming-Ta CHOU
  • Publication number: 20190341544
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
    Type: Application
    Filed: June 4, 2018
    Publication date: November 7, 2019
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Patent number: 10468340
    Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100%? about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun
  • Patent number: 10466435
    Abstract: A dual lens driving apparatus includes a holder, a metal yoke, a carrier, a coil, a first magnet, a first elastic element and a second elastic element. The metal yoke is corresponding to the holder and includes a front end which includes a plate surface and a plurality of step portions, and a level difference is between each of the step portions and the plate surface. The carrier is movably disposed in the metal yoke. The coil is disposed around the carrier. The first magnet is disposed in the metal yoke. The first elastic element is assembled on a side of the carrier facing the front end of the metal yoke. The second elastic element is assembled on another side of the carrier facing the holder.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 5, 2019
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Te-Sheng Tseng, Wen-Hung Hsu, Yung-Chun Kang