Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727068
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
  • Patent number: 10727135
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10727298
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20200230105
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 23, 2020
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Publication number: 20200230149
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 23, 2020
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Publication number: 20200220098
    Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. The thin-film circuitry may be formed in thin-film transistor (TFT) layers and the organic light-emitting diodes may include anodes and cathodes and an organic emissive layer formed over the TFT layers between the anodes and cathodes. The organic emissive layer may be formed via chemical evaporation techniques. The display may include moisture blocking structures such as organic emissive layer disconnecting structures that introduce one or more gaps in the organic emissive layer during evaporation so that any potential moisture permeating path from the display panel edge to the active area of the display is completely terminated.
    Type: Application
    Filed: October 31, 2019
    Publication date: July 9, 2020
    Inventors: Tsung-Ting Tsai, Abbas Jamshidi Roudbari, Chuan-Sheng Wei, HanChi Ting, Jae Won Choi, Jianhong Lin, Nai-Chih Kao, Shih Chang Chang, Shin-Hung Yeh, Takahide Ishii, Ting-Kuo Chang, Yu Hung Chen, Yu-Wen Liu, Yu-Chuan Pai, Andrew Lin
  • Patent number: 10705283
    Abstract: A light source module including a first light guide plate, a first light source, a second light guide plate, a second light source, and a turning film is provided. The first light guide plate and the second light guide plate are sequentially stacked up. The second light guide plate is disposed between the first light guide plate and the turning film. The turning film has a plurality of prism columns, the prism columns face the second light guide plate. The first light guide plate includes a first light exiting surface, the first light exiting surface is located at a side facing the turning film and has a plurality of lenticular lens structures. The lenticular lens structures are arranged along a first direction and extended along a second direction perpendicular to the first direction. Besides, a display apparatus is also provided.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 7, 2020
    Assignee: Nano Precision Taiwan Limited
    Inventors: Kuan-Wen Liu, Chi-Lung Lee, Hao-Jan Kuo
  • Patent number: 10700176
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 10700013
    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wen Liu, Sebastian T. Ventrone, Adam C. Smith, Janice M. Adams, Nazmul Habib
  • Patent number: 10698954
    Abstract: Various embodiments include a classification platform system. A user can define a classification experiment on the classification platform system. For example, the user can define an input data space by selecting at least one of data sources interfaced with the classification platform system and defining a workflow configuration including a directed graph (DG) connecting a plurality of transformation blocks to represent an experiment workflow. The DG can specify how one or more outputs of each of the transformation blocks are fed into one or more other transformation blocks. The DG can be executed by various types of computation platforms. The classification platform system can schedule the experiment workflow to be executed on a distributed computation platform according to the input data space and the workflow configuration.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 30, 2020
    Assignee: Facebook, Inc.
    Inventors: Szymon Piechowicz, Barak Reuven Naveh, Annie Hsin-Wen Liu, Ashish Gupta
  • Publication number: 20200194062
    Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.
    Type: Application
    Filed: October 17, 2019
    Publication date: June 18, 2020
    Inventors: Wen LIU, Hongjin He
  • Publication number: 20200188397
    Abstract: The present invention provides for compounds of Formula I-I and embodiments and salts thereof for the treatment of diseases (e.g., neurodegenerative diseases). R1, R2, R3, X1, X2, A and Cy variable in Formula I-I all have the meaning as defined herein.
    Type: Application
    Filed: October 28, 2019
    Publication date: June 18, 2020
    Applicant: Genentech, Inc.
    Inventors: Anthony Estrada, Liting Dong, Kevin X. Chen, Paul Gibbons, Malcolm Huestis, Terry Kellar, Wen Liu, Changyou Ma, Joseph Lyssikatos, Alan Olivero, Snahel Patel, Daniel Shore, Michael Siu
  • Patent number: 10679990
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10679900
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20200173958
    Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.
    Type: Application
    Filed: May 16, 2019
    Publication date: June 4, 2020
    Inventors: Katherine H. Chiang, Jui-Cheng Huang, Ke-Wei Su, Tung-Tsun Chen, Wei Lee, Pei-Wen Liu
  • Patent number: 10672742
    Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang Wu, Chun-Fu Cheng, Chung-Cheng Wu, Yi-Han Wang, Chia-Wen Liu
  • Patent number: 10672674
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Patent number: 10671666
    Abstract: A pattern based audio searching method includes labeling a plurality of source audio data based on patterns to obtain audio label sequences of the source audio data; obtaining, with a processing device, an audio label sequence of target audio data; determining matching degree between the target audio data and the source audio data according to a predetermined matching rule based on the audio label sequence of the target audio data and the audio label sequences of the source audio data; and outputting source audio data having matching degree higher than a predetermined matching threshold as a search result.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Feng Jin, Qin Jin, Wen Liu, Yong Qin, Xu Dong Tu, Shi Lei Zhang
  • Publication number: 20200167428
    Abstract: A computer-implemented method for utilizing external knowledge and memory networks in a question-answering system includes receiving, from a search engine of a question-answering system, one or more search results based on a search query associated with a question submitted via a user interface associated with a computing device, analyzing the one or more search results to generate search evidence as a source of external knowledge for generating an answer to the question, the search evidence including one or more titles and one or more corresponding text snippets, encoding the search evidence and the search query to generate vectors stored in a memory network, obtaining a final vector representation based on the encoding, and decoding the final vector representation to obtain the answer to the question.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 28, 2020
    Inventors: Peng Wang, Shi Lei Zhang, Wen Liu, Feng Jin, Qin Shi, Yong Qin
  • Patent number: 10665718
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung