Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

Abstract: The present invention provides a facial mask composition, comprising by weight percentage, the following ingredients: (a) 0.01% to 30% of emollient oil; (b) 0.01% to 20% of moisturizer; (c) 0.01% to 10% of thickening polymer; (d) 0.01% to 10% of skin conditioner; and (e) 10% to 90% of deionized water; wherein, the skin conditioner comprises, by weight parts: Radix Astragali 20, Aloe vera 30, Radix Angelicae Dahuricae 20 and Poria cocos 30.

Abstract: The presently described compounds relate to the treatment of diabetes and/or hyperglycemia. More particularly, the described compounds relate to acylated insulin compounds that lower blood glucose, pharmaceutical compositions containing such compounds, therapeutic uses of such compounds, and an intermediate compound used to make the acylated insulin compounds.

Abstract: A touch display panel includes a first sensing matrix and a second sensing matrix. The first sensing matrix includes a plurality of grid units and a first switch unit. The grid units are arranged in matrix, wherein each grid unit includes at least one first electrode. The first switch unit includes a plurality of switches, and the switches are disposed between adjacent grid units. Wherein, the control end of the switches is configured to receive a first controlling signal, and one end of each of the switches is configured to output a sensing signal. The second sensing matrix includes at least one second electrode, and is configured to receive a common signal. The second sensing matrix includes a plurality of opening units, and each opening unit overlaps with the open area of each pixel circuit in a vertical projection direction of the first substrate.

Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.

Abstract: Provided in the present invention are a class of Lincomycin biosynthetic intermediates and a preparation method and use thereof. Specifically provided are Lincomycin biosynthetic intermediates obtained from the genetic modification of a Lincomycin producing bacterium, and a method for the production thereof through fermentation and purification through separation.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: A method and a detection circuit for selecting a touch detection time are provided. The method for selecting a touch detection time includes the following steps: detecting a noise signal of a touch panel in a first display frame period; determining whether signal strength of the noise signal in a first time segment in the first display frame period is greater than a first noise threshold; and when the signal strength of the noise signal in the first time segment in the first display frame period is less than the first noise threshold, performing touch control in a second time segment in a second display frame period corresponding to the first time segment.

Abstract: A semiconductor structure includes a silicon control rectifier (SCR) region and a NPN region adjacent to the SCR region. The silicon control rectifier (SCR) region includes a first p-well region, a first n-well region surrounded by the first p-well region and a first P+ region in the first p-well region and spaced apart from the first n-well region. The NPN region includes a second p-well region, a first N+ region, a second N+ region and a second P+ region. The first N+ region is coupled to the second p-well region and an electrostatic discharge source. The second N+ region is coupled to the second p-well region and spaced apart from the first N+ region. The second P+ region is disposed in the second p-well region and equipotentially connected to the first P+ region in the first p-well region.

Abstract: A fixed-line trimmer head for a rotary trimmer device includes the upper portion having a periphery, wherein the upper portion has a plurality of openings spaced from the periphery; and a plurality of mechanisms. Each mechanism can hold a strip of line and includes a post portion disposed through one of the openings in the upper portion, and a flange disposed at one end of the post portion and sandwiched between the upper portion and lower portion of the trimmer head to prevent vertical movement of the mechanism. The post portion includes two line channels, each line channel defining a passageway to receive the same strip of line, wherein at least one of the line channels is curved such that any portion of the strip of line being received through the passageway of that line channel is bent at that portion of the strip of line away from the second line channel while passing through that at least one line channel that is curved.

Abstract: A hearing diagnosis device and a hearing diagnosis method are provided. The device includes a storage unit, an otoacoustic emission detecting module, and a hearing diagnosis management module. The storage unit stores a hearing diagnosis image sample database and a hearing information sample database. The otoacoustic emission detecting module is configured to perform an otoacoustic emission detecting operation by playing a test audio to an ear of a user to obtain a first hearing diagnosis image corresponding to the ear. The hearing diagnosis management module is configured to perform a hearing diagnosis operation according to the first hearing diagnosis image, a plurality of hearing diagnosis image samples of the hearing diagnosis image sample database, and a plurality of hearing information samples, respectively corresponding to the hearing diagnosis image samples, of the hearing information sample database, so as to determine first hearing information of the ear.

Abstract: Disclosed is a flue gas purification tower, comprising a tower body, at least one gas inlet (1) disposed at the bottom of the tower body, at least one gas outlet (2) disposed at the top of the tower body, at least one active coke layer (3) located inside the tower body, and a baffle plate (4) arranged in a place where the flow direction of the flue gas from the gas inlet changes. The baffle plate (4) is a straight plate, an arc plate, a straight-and-arc plate or a straight-arc-straight plate, wherein the straight-and-arc plate comprises a straight segment and an arc segment connected with each other; and the straight-arc-straight plate comprises a straight segment in the vertical direction, a straight segment in the horizontal direction, and an arc segment connected between the two straight segments.

Abstract: This application relates to the field of communications technologies, and in particular, to a profile download technology. In a profile download method, a primary device obtains an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID; receives the profile download information from the mobile operator server; and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.

Abstract: A gate driver and a touch display apparatus thereof are provided. The gate driver includes a plurality of shift registers and at least one loop circuit. The shift registers provide multiple gate signals to a touch display module. The loop circuit is coupled in series with the shift registers and receives at least one touch switching signal to set a loop time of the loop circuit. The touch display module performs at least one touch scan during the loop time.

Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.

Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.