Patents by Inventor Wen Lo

Wen Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7151317
    Abstract: A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: December 19, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shin-Hua Chao, Jian-Wen Lo
  • Publication number: 20060251730
    Abstract: An anti-microbial sanitary ware includes a substrate, and an anti-microbial film formed on the substrate and including a protective layer and anti-microbial metal particles that are dispersed in the protective layer. The protective layer is made from a compound selected from the group consisting of metal nitrides and metal carbides. The anti-microbial metal particles are made from a metal selected from the group consisting of silver, zinc, and copper.
    Type: Application
    Filed: July 12, 2006
    Publication date: November 9, 2006
    Inventor: Wen Lo
  • Publication number: 20060199443
    Abstract: A display device (20) includes a display panel (25) and a rigid-flexible printed circuit board (2) electrically connected to the display panel. The rigid-flexible printed circuit board has the characteristics of both a rigid and a flexible printed circuit board, thereby reducing the size of the rigid-flexible printed circuit board and the amount of connectors required. Additionally, the cost of the rigid-flexible printed circuit board is less than that of a conventional printed circuit board.
    Type: Application
    Filed: December 23, 2005
    Publication date: September 7, 2006
    Inventor: Wen Lo
  • Publication number: 20060197191
    Abstract: A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on the circuitry unit and exposes the bonding pads. The redistribution layer of a Ti/Cu/Ti multi-layered structure is disposed on the first passivation layer, and is electrically connected with the bonding pads. In addition, the redistribution layer of a Ti/Cu/Ti multi-layered structure has excellent conductivity such that electrical characteristics of the chip structure are enhanced effectively.
    Type: Application
    Filed: December 13, 2005
    Publication date: September 7, 2006
    Inventors: Mon-Chin Tsai, Chi-Yu Wang, Jian-Wen Lo, Shao-Wen Fu
  • Publication number: 20060199306
    Abstract: A chip structure and the manufacturing process thereof are provided. The feature of the present application is that the chip structure has a first passivation layer covering a substrate of the chip and exposing each of bonding pads and a portion of the substrate surface, and a second passivation layer covering the sidewalls of the first passivation layer and the portion of substrate surface exposed by the first passivation layer, to prevent moisture infiltration from the edge of the substrate. Therefore, the reliability of the chip structure is enhanced.
    Type: Application
    Filed: December 15, 2005
    Publication date: September 7, 2006
    Inventors: Mon-Chin Tsai, Jian-Wen Lo, Shao-Wen Fu, Chi-Yu Wang
  • Patent number: 7095476
    Abstract: A liquid crystal module has a liquid crystal panel and a flexible printed circuit board. The liquid crystal panel has a substrate and an indium tin oxide (ITO) film on the substrate. A flexible printed circuit board has an insulating layer on which a lower conductive layer, a second protective layer, an upper conductive layer and a first protective layer are stacked in sequence. The lower conductive layer is electrically connected to predetermined portions of the lower conductive layer and has a conductive portion, which is unshielded by the insulating layer. The flexible printed circuit board is bonded to the liquid crystal panel with the insulting layer stacked on the indium tin oxide film and the pins of the indium tin oxide film electrically connected to the conductive portion of the lower conductive layer.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: August 22, 2006
    Assignee: Wintek Corporation
    Inventors: Chin-Wen Lo, Ming-Chuan Lin, Wei-Wen Hsueh, Yu-Jen Tsai
  • Patent number: 7076870
    Abstract: A surface-mount package for an oscillator crystal blank is made from a metal sheet substrate. Half-etched cavities are formed on one side of the sheet. The half-etched cavities are filled in with an insulator. The center of the insulator is drilled until metal is reached, leaving insulator on the sidewalls of the resulting drilled via. The bottom of the drilled via is plated with a contact metal such as nickel-gold, and then the entire drilled via is filled in with metal such as copper to form via-metal. An external metal surface-mount pad is formed on the surface of each via-metal. The metal sheet is flipped over, and a larger inner cavity etched through until the contact metal over the via-metal is reached. Conductive epoxy is placed on the contact metal, and electrodes on the crystal blank are attached to conductive epoxy.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: July 18, 2006
    Assignee: Pericom Semiconductor Corp.
    Inventor: Wen-Lo Hsieh
  • Publication number: 20060082715
    Abstract: A liquid crystal module has a liquid crystal panel and a flexible printed circuit board. The liquid crystal panel has a substrate and an indium tin oxide (ITO) film on the substrate. A flexible printed circuit board has an insulating layer on which a lower conductive layer, a second protective layer, an upper conductive layer and a first protective layer are stacked in sequence. The lower conductive layer is electrically connected to predetermined portions of the lower conductive layer and has a conductive portion, which is unshielded by the insulating layer. The flexible printed circuit board is bonded to the liquid crystal panel with the insulting layer stacked on the indium tin oxide film and the pins of the indium tin oxide film electrically connected to the conductive portion of the lower conductive layer.
    Type: Application
    Filed: October 15, 2004
    Publication date: April 20, 2006
    Applicant: Wintek Corporation
    Inventors: Chin-Wen Lo, Ming-Chuan Lin, Wei-Wen Hsueh, Yu-Jen Tsai
  • Publication number: 20060032051
    Abstract: A surface-mount package for an oscillator crystal blank is made from a metal sheet substrate. Half-etched cavities are formed on one side of the sheet. The half-etched cavities are filled in with an insulator. The center of the insulator is drilled until metal is reached, leaving insulator on the sidewalls of the resulting drilled via. The bottom of the drilled via is plated with a contact metal such as nickel-gold, and then the entire drilled via is filled in with metal such as copper to form via-metal. An external metal surface-mount pad is formed on the surface of each via-metal. The metal sheet is flipped over, and a larger inner cavity etched through until the contact metal over the via-metal is reached. Conductive epoxy is placed on the contact metal, and electrodes on the crystal blank are attached to conductive epoxy.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Applicant: PERICOM SEMICONDUCTOR CORP.
    Inventor: Wen-Lo Hsieh
  • Publication number: 20060032037
    Abstract: An assembling device and method for mounting a second plate to a first plate is described. The assembling device is an alignment jig includes a first carrier plate having a first air channel and a first carrier area and a second carrier plate having a second air channel and a second carrier area. The first air channel is linked to the first carrier area and the first plate is on the first carrier area. The second carrier plate and the first carrier plate are joined together through a pivot and the second carrier plate is stacked over the first carrier plate. The second air channel is linked to the second carrier area. The second plate is over the second carrier area. The second carrier plate or the first carrier plate has a third air channel and the corresponding second or third plate has an opening exposing the third air channel.
    Type: Application
    Filed: August 13, 2004
    Publication date: February 16, 2006
    Inventors: Dar-Wen Lo, Chang-An Chen
  • Publication number: 20050199991
    Abstract: A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.
    Type: Application
    Filed: November 9, 2004
    Publication date: September 15, 2005
    Inventors: Shin-Hua Chao, Jian-Wen Lo
  • Publication number: 20050204420
    Abstract: The invention relates to transformed plant cells and plants having a novel nucleic acid and protein sequences from the mung bean Vigna radiata. The nucleic acid sequence, isolated from a bruchid resistant mung bean line, encodes a thionin-like protein with biocidal properties.
    Type: Application
    Filed: February 14, 2005
    Publication date: September 15, 2005
    Inventors: Ching-San Chen, Gan-Hong Chen, Li-Wen Lo
  • Publication number: 20050095750
    Abstract: A process for manufacturing transparent semiconductor packages is disclosed. A wafer having an active surface and a back surface is provided. A plurality of first redistribution lines are formed on the active surface of the wafer to connect the bonding pads of the chips. A transparent polymer is formed over the active surface of the wafer to cover the first redistribution lines. A plurality of first grooves are formed corresponding to the scribe lines and in the back surface of the wafer. Preferably, a back coating is then formed over the back surface to fill the first grooves. Next, a plurality of second grooves are formed corresponding to the first grooves and through the back coating such that the first redistribution lines have exposed portions. A plurality of second redistribution lines on the back coating can extend to the exposed portions of the corresponding first redistribution lines for connecting solder balls on the back surface.
    Type: Application
    Filed: September 24, 2004
    Publication date: May 5, 2005
    Inventors: Jian-Wen Lo, Shin-Hua Chao, Chia-Yi Hu
  • Publication number: 20040183179
    Abstract: A package structure for a multi-chip integrated circuit (IC) is disclosed and the structure includes substrate having a position for bonding with chips for chip-bonding and having at least a hole for the passage of a gold wire in the course of wire-bonding, a first chip attached to the substrate with a chip bonding agent and being wire-bonded on the substrate and the chip bonding position being opposite to the 2nd chip with the substrate in-between, and the gold wire of the wire-bonding passed through the hole of the substrate from the substrate bonding pad at the substrate and on the same lateral side of the second chip and being connected to the pin pad of the first chip, at least a second chip being flip-chip bonded onto the substrate and the bonding position being at different sides of the bonding between the substrate and the first chip, and a package body including filler of the second chip extended to cover the hole of the substrate and the first chip and the gold wire connected to the substrate and th
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Inventors: Wen-Lo Shieh, Fu-Yu Huang, Chia-Chieh Hu, Ning Huang, Hui-Pin Chen, Chang-Ming Hsin, Shu-Wan Lu, Tou-Sung Wu, Chih-Yu Tsai, Yu-Tang Su, Mei-Hua Chen, Chia-Ling Lu, Yu-Ju Wang
  • Publication number: 20040082159
    Abstract: A fabrication method for solder bump pattern of rear section wafer package is disclosed and the method includes the steps of: (a) pattern-etching the wafer at a passivation layer for the positioning of the solder bump; (b) depositing the entire under bump metal layer,
    Type: Application
    Filed: March 10, 2003
    Publication date: April 29, 2004
    Inventors: Wen-Lo Shieh, Fu-Yu Huang, Ning Huang, Hui-Pin Chen, Shu-Wan Lu, Zhe-Sung Wu, Chih-Yu Tsai, Mei-Hua Chen, Chia-Ling Lu, Yu-Ju Wang, Yu-Chun Huang, Tzu-Lin Liu, Wen-Tsung Weng, Ya-Hsin Tseng
  • Publication number: 20040082174
    Abstract: A method of wire bonding of a semiconductor device for resolving oxidation of copper bonding pad is disclosed. The method comprises the steps of exposing the copper bonding pad of a wafer which has been completed with semiconductor circuit fabrication; covering the copper bonding pad of the wafer with a protective anti-oxidization film which will be vaporized when heated; performing wire bonding directly without requiring the removal of the protective film, employing ultrasonic vibration energy, pressurizing deformation energy and heat energy in the course of bonding to vaporize the protective film so that the metal wire and the copper pad form a large area intermetallic compound layer for bonding.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 29, 2004
    Inventors: Wen-Lo Shieh, Fu-Yu Huang, Ning Huang, Hui-Pin Chen, Shu-Wan Lu, Zhe-Sung Wu, Chih-Yu Tsai, Mei-Hua Chen, Chia-Ling Lu, Yu-Ju Wang, Yu-Chun Huang, Tzu-Lin Liu, Wen-Tsung Weng, Ya-Hsin Tseng
  • Publication number: 20040032021
    Abstract: An improved structure of heat dissipation fin for prevention of glue-overflowing in semiconductor packaging includes a substrate and a chip bonding module, wherein the heat dissipation fin is a thin housing structure having a bottom flat section and the center position is provided with a protruded section, forming into a covering body to cover the chip and the bonding body, the top section of the protruded section is provided with a first stepped platform and the inner edge of the platform is further formed into bottom recess structure and the wall thereof is then formed vertically into a raised second stepped protruded ring, and the center at the inner edge of the second stepped protruded ring is formed into a top recessed face, thereby the first stepped ring platform and the second stepped ring platform urge the top face of the top edge of the mold to form into a structure to block the packaging adhesive such that the adhesive will not overflow into the center position of the heat dissipation fin.
    Type: Application
    Filed: May 14, 2003
    Publication date: February 19, 2004
    Inventors: Wen-Lo Shieh, Hung Hjing
  • Publication number: 20030160320
    Abstract: A high heat dissipation micro-packaging body for semiconductor chip is disclosed and the body comprises lead frame having an etched recessed platform for a chip seat, the surrounding area of the platform being groove having a plurality of supporting belt connected to the lead frame; a substrate having a plurality of pins, corresponding to the position of the groove, for connection with gold lines; a chip being bonded to the chip seat of the lead frame with bonding agent, the gold lines being mounted at the predetermined electrically connection pin positions of the substrate and a pin pad so as to function as output, and heat energy evolved in the course of operation of the chip is dissipated from the chip seat via the support belt to other regions of the lead frame for dissipation.
    Type: Application
    Filed: July 18, 2002
    Publication date: August 28, 2003
    Inventors: Wen-Lo Shieh, Chia-Ming Yang, Shu-Fen Liang, Yen-Shu Hsieh, Shu-Min Chou, Chun-Lung Tseng
  • Publication number: 20030160316
    Abstract: An open-typed multi-chip stack-packaging is disclosed and the packaging comprises a substrate having a first surface and a second surface, at least a through opening formed on the substrate, and including at least two layers of circuitry to electrically transmit signals; at least a first chip positioned on the upper section of the opening of the first surface and a plurality of protruded blocks being soldered onto the circuitry on the first surface of the substrate at the external region of the substrate for electrically connection; at least a second chip stacked onto the first chip and the second chip being connected electrically to the circuitry of the first surface with gold lines; at least a third chip positioned at the lower section of the opening of the second surface and having a size smaller than the first chip, and a plurality of protruded blocks being used to electrically bond with the center position of the first chip, and adhesive being used to fill the first chip and the third chip, and the regio
    Type: Application
    Filed: January 13, 2003
    Publication date: August 28, 2003
    Inventors: Wen-Lo Shieh, Fu-Yu Huang, Ning Huang, Hui-Pin Chen, Shu-Wan Lu, Tou-Sung Wu, Chih-Yu Tsai, Mei-Hua Chen, Chia-Ling Lu, Yu-Ju Wang
  • Patent number: D514427
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: February 7, 2006
    Inventor: Chi-Wen Lo