Patents by Inventor Wen Su

Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160111327
    Abstract: A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 21, 2016
    Inventors: Ya-Lien Lee, Hung-Wen Su, Kuei-Pin Lee, Yu-Hung Lin, Yu-Min Chang
  • Patent number: 9312690
    Abstract: A protective circuit is provided. The protective circuit includes a charging unit, a voltage regulating unit, and a comparing unit. The charging unit receives a rise signal and an over-current signal, and outputs a first reference voltage. The voltage regulating unit receives the first reference voltage and adjusts an output voltage according, to the first reference voltage and a feedback voltage. The comparing unit receives the feedback voltage and compares the feedback voltage with a first threshold voltage to determine whether to output the rise signal to the charging unit.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: April 12, 2016
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventor: Ting-Wen Su
  • Publication number: 20160064332
    Abstract: A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: Chen-Yuan Kao, Hung-Wen Su, Chih-Yi Chang, Liang-Yueh Ou Yang
  • Publication number: 20160062417
    Abstract: A wearable electronic device includes a device body and a wearing element. The wearing element is connected to the device body. The device body includes a conductive upper cover, a conductive lower cover, an insulating frame and a circuit system. The insulating frame is disposed between the conductive upper cover and the conductive lower cover and forms an accommodating space therewith. The circuit system is disposed in the accommodating space. The conductive upper cover has a first feeding point. The conductive lower cover has a second feeding point. The circuit system is coupled to the first feeding point and the second feeding point respectively.
    Type: Application
    Filed: April 16, 2015
    Publication date: March 3, 2016
    Inventors: Fang-Hsien Chu, Chih-Chung Lin, Yi-Ting Hsieh, Chia-Min Chuang, Saou-Wen Su, Bin-Chyi Tseng, Jian-Sheng Hsieh, Tsung-Chieh Yen
  • Publication number: 20160057148
    Abstract: Disclosed are systems, apparatus, methods, and computer-readable storage media for providing access to an online social network. The online social network can be specific to an organization having one or more internal users. In some implementations, a request message is received from a requesting user to access social network data of the online social network. The requesting user is identified as an external user of the organization, and it is determined that the requesting user has an authorized status. Access to only a portion of the social network data is provided to the authorized requesting user.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: Michael Scott Micucci, Aditya Sesha Kuruganti, Theodore James Summe, Kedar Doshi, Leonard Gestrin, Sanjaya Lai, George Wen Su
  • Patent number: 9269612
    Abstract: An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Chen, Wen-Jiun Liu, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Patent number: 9240378
    Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: January 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ken-Yu Chang, Hung-Wen Su
  • Patent number: 9225053
    Abstract: A multi-band antenna includes a grounding portion, a main radiating portion, and a shielding wall. The main radiating portion includes a first radiating portion having a first feed end and a second radiating portion having a second feed end. The first and second radiating portions are structurally symmetrical. The main radiating portion and the shielding wall are arranged on opposite sides of the grounding portion.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 29, 2015
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Tzu-Chieh Hung, Saou-Wen Su
  • Publication number: 20150371943
    Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer includes metal ions.
    Type: Application
    Filed: August 27, 2015
    Publication date: December 24, 2015
    Inventors: Hung-Wen SU, Shih-Wei CHOU, Ming-Hsing TSAI
  • Patent number: 9218970
    Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
  • Patent number: 9214383
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Jiun Liu, Chien-An Chen, Ya-Lien Lee, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 9209073
    Abstract: Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethylaminoborane.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Yueh Ou Yang, Chih-Yi Chang, Chen-Yuan Kao, Hung-Wen Su
  • Publication number: 20150333012
    Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: KEN-YU CHANG, HUNG-WEN SU
  • Patent number: 9178753
    Abstract: Disclosed are systems, apparatus, methods, and computer-readable storage media for providing access to an online social network. The online social network can be specific to an organization having one or more internal users. In some implementations, a request message is received from a requesting user to access social network data of the online social network. The requesting user is identified as an external user of the organization, and it is determined that the requesting user has an authorized status. Access to only a portion of the social network data is provided to the authorized requesting user.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: November 3, 2015
    Assignee: salesforce.com, inc.
    Inventors: Michael Scott Micucci, Aditya Sesha Kuruganti, Theodore James Summe, Kedar Doshi, Leonard Gestrin, Sanjaya Lai, George Wen Su
  • Publication number: 20150311151
    Abstract: A method for forming a semiconductor device includes forming a first dielectric layer overlying a substrate, forming at least a first opening in the first dielectric layer, forming a conformal dense layer lining the at least first opening in the first dielectric layer, forming a barrier layer overlying the conformal dense layer, forming a conductive feature in the at least first opening, removing a portion of the first dielectric layer between any two adjacent conductive features to form a second opening, wherein the second opening exposes the conformal dense layer between the two adjacent conductive features, and depositing between the two adjacent conductive features a second dielectric layer having an air gap formed therein.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 29, 2015
    Inventors: Chih-Chien Chi, Hung-Wen Su
  • Patent number: 9166468
    Abstract: A voltage regulator circuit includes a soft start module, a pulse width modulation (PWM) module, and a voltage regulator module. The soft start module is used to receive a current feedback voltage corresponding to an input current, and compare the current feedback voltage with a comparison voltage, so as to output a switching signal. The PWM module is used to receive a clock signal and the switching signal, and determine a first PWM signal and a second PWM signal outputted by the PWM module is a high voltage level or a low voltage level according to the clock signal and the switching signal. The voltage regulator module is used to receive and adjust an output voltage corresponding to the first PWM signal and the second PWM signal.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 20, 2015
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventors: Ting-Wen Su, Yu-Chuan Lin
  • Patent number: D744920
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: December 8, 2015
    Assignee: Gogoro Inc.
    Inventors: Chien-Chih Weng, Hsin-Wen Su
  • Patent number: D752490
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 29, 2016
    Assignee: GOGORO INC.
    Inventors: Hok-Sum Horace Luke, Chien-Chih Weng, Hsin-Wen Su, Song-Fu Wang
  • Patent number: D754387
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 19, 2016
    Assignee: GOGORO INC.
    Inventors: Hok-Sum Horace Luke, Chien-Chih Weng, Hsin-Wen Su, Song-Fu Wang
  • Patent number: D754893
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 26, 2016
    Assignee: GOGORO INC.
    Inventors: Hok-Sum Horace Luke, Chien-Chih Weng, Hsin-Wen Su, Song-Fu Wang