Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract: A method dynamically adjusts a log level of a transaction. The method includes: buffering the most detailed logs of a transaction having highest log level into a memory; checking if all dependency-defined transactions within a dependency list/tree for the transaction are completed; and, in response to the completion of all dependency-defined transactions within the dependency list/tree for the transaction, obtaining a log filter level for the transaction in association with the transaction results (success/failure) of dependency-defined transactions, wherein the log filter level is a new log level for the transaction.

Abstract: A stand-alone multi-band antenna includes an antenna ground plate, a shielding metal wall, a first radiating unit, and a signal feed-in source. The first radiating unit connected to at least one side of the antenna ground plate and located above the antenna ground plate is an antenna structure generating the fringing-field. The first radiating unit provides a first operating band and a second operating band. The shielding metal wall is connected to a plurality of the adjacent sides of the antenna ground plate, and the height thereof is larger than or equal to that of the first radiating unit, therefore limiting the fringing-field of the first radiating unit within the stand-alone multi-band antenna. The signal feed-in source has a signal feed-in point and a ground point. The signal feed-in point is electrically connected to the first radiating unit, and the ground point is electrically connected to the shielding metal wall.

Abstract: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N2 flow at least 20 sccm. The structure offers low contact resistance (Rc) and tight Rc distribution.

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract: A motor driving apparatus is applied to a fan and motor mechanism and a voltage supply unit. The motor driving apparatus includes a motor driving unit, a voltage division resistor, a first resistor, a first switch unit, a second resistor, a second switch unit, a third resistor, a third switch unit, a transistor switch, and a pulse width modulation unit. The first switch unit, the second switch unit, and the third switch unit are configured to select the rotational speed upper limitation of the fan and motor mechanism for suppressing noise.

Abstract: An unbalanced antenna includes a non-conductive substrate having one short edge, and two long edges connected respectively to two opposite ends of the short edge and parallel to each other, and an unbalanced antenna disposed proximate to the short edge of the non-conductive substrate and having a ground portion. A ground plane has side edges extending along the long edges of the non-conductive substrate, and is electrically coupled with the ground portion. The length of the ground plane is longer than a quarter of an equivalent wavelength corresponding to an operating frequency of the unbalanced antenna. A pair of choke sleeve structures are symmetrically disposed at opposite sides of the ground plane and spaced apart from the unbalanced antenna by a quarter of an equivalent wavelength corresponding to the operating frequency. Each choke sleeve structure has one end connected to the ground plane, and the other end extending in a direction away from the unbalanced antenna.

Abstract: A hybrid multi-antenna system includes a system circuit board, an antenna substrate, at least a dipole antenna, and at least a monopole-slot antenna. The system board has at least a system ground plate, and the system ground plate is served as a reflector of the hybrid multi-antenna system. The antenna substrate and the system ground plate have a first distance therebetween. The dipole antenna having a first signal feed-in source and the monopole-slot antenna having a second signal feed-in source respectively provide a first and second operating band, and they are on a surface of the antenna substrate. The monopole-slot antenna is located nearby the dipole antenna. The monopole-slot antenna and the dipole antenna have a second distance therebetween. The first and second signal feed-in sources are vertical to each other, and have the phase difference of 90°.

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract: Providing efficient data replication for a transaction processing server is provided. A notification is received from the transaction processing server which completes a transaction of a message. The notification includes a message digest and a message identifier. The message identifier in the received notification is compared with a stored message identifier. In response to a match of the comparing of the message identifier, the message digest in the received notification is compared with a stored message digest. In response to a match of the comparing of the message digest, a stored input message is directly stored in a physical storage.

Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.

Abstract: One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure.

Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.

Abstract: Presented herein is a method of processing a device, comprising providing an electroplating bath having a leveler, the leveler having a total nitrogen-to-total carbon (TN/TOC) ratio of about 15% or less, bringing a substrate into contact with the electroplating bath, the substrate having a recess formed therein and electroplating the substrate to create a feature substantially free of voids in the substrate recess. Electroplating the substrate is performed for a time period about as long as an electrical response peak of the leveler, and optionally for at least 30 seconds. The leveler may optionally have at least one ingredient free of nitrogen and having a leveling functionality. One ingredient may be a benzene ring free of nitrogen. The leveler TN/TOC ratio is between about 3% and about 15%.

Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract: A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.

Abstract: A web conferencing server, including a conferencing module, a monitoring module and a control module, is provided. The conferencing module enables a plurality of participants to attend a web conference and further provides a first participant with a conference right, which allows the first participant to issue a conference command. The monitoring module monitors the status of the first participant in order to generate a status notification. In response to the status notification, the control module issues a control command to the conferencing module, to withhold the conference right from the first participant.