Abstract: A patterned gold bump structure for a semiconductor chip comprises at least a patterned gold bump disposed on an insulating layer of a semiconductor chip, wherein the gold bump is used as a circuit component or a passing line. In some embodiments, the circuit component is a capacitor, a resistor, or an inductor.

Abstract: A chip with a bump structure comprises a chip, a plurality of pads and a plurality of bumps. The chip includes a microcircuit fabricated by integrated circuit technique. The pads are metallized portions of the chip for electrical connection. The bumps are metal bulges on the pads of the chip for electrically connecting the pads with the terminals of other components. The bumps are arranged in a horizontal direction, and each of the bumps include a first section and a second section, wherein the first section and the second section are electrically connected to each other along a vertical direction. The first section electrically contacts the corresponding pad. The size of the second section in the horizontal direction is larger than that of the first section. The second section is used for electrically connecting the chip to other components. The first section and the second section of adjacent bumps are interlaced.

Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Abstract: A polarization conversion system suited for LCD or LCoS-based projection applications is disclosed. The present invention polarization conversion system encompasses a light pipe with a rectangular light tunnel therein defined by four side reflection mirrors. A front reflection with an aperture thereon is mounted on an entrance face of the light pipe. A first polarization beam splitter is mounted on an exit face of the light pipe. A retardation plate, which is perpendicular to the exit face, is situated atop the first polarization beam splitter. A reflection mirror is situated atop the retardation plate. A second polarization beam splitter is mounted under the first polarization beam splitter and is opposite to the retardation plate.

Abstract: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.

Abstract: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: In one embodiment, one or more gateways sniff the voice channel during the voice mode. If it is determined that V.8bis signals are being initiated, then the gateway breaks these exchanges by suppressing such signaling, thereby avoiding the above-described detrimental effects. Modem relay communications then are allowed to proceed. Briefly, the method and apparatus involve monitoring a call during a voice mode phase for an initiating signal representative of the defined signaling, the monitoring being performed by a local gateway and, if such an initiating signal is detected during the monitoring, then suppressing such detected signaling in such manner that the signaling does not reach the remote gateway. Preferably, the monitoring is for an initiating signal characterized by a dual tone of defined frequency and duration of approximately 1375 Hz and 2002 Hz for a duration of approximately 400 ms or 285 ms, in agreement with the ITU-T Recommendation V.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, which neighbor each other, and a single material region. The insulator is harder than the conductor.

Abstract: A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band structure engineering is used to alter the band structure between a bulk part of the device and another part of the device supporting the measurement current.

Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

Abstract: Disclosed is a method for producing a double-crosslinked hyaluronate material. A hyaluronic acid or a salt thereof is sequentially reacted with an epoxide compound and a carbodiimide compound to produce a more biodegradation-resistant hyaluronate material. The HA acid is preferably reacted with the carbodiimide first, and more preferably in a mixed solvent including water and an organic solvent, such as ketone.

Abstract: A position-adjusting mechanism of an optical engine comprises a base, an adjusting board, two adjusting devices, two fastening devices, and a universal bearing. The adjusting board is set on the base and has two arc slots and two screw holes formed thereon. The adjusting devices are respectively screwed in one of the screw holes and set against the base. One end of the fastening device is inserted through one of the arc slots and is fixed on the base, and the other end of each fastening device is used to press the adjusting board towards the base. The universal bearing is located between the base and the adjusting board and serves as a pivot for rotating the adjusting board against the base.

Abstract: Methods and apparatuses for protecting charge trapping memory cells from over-erasing in response to an erase command are disclosed.

Abstract: A T-shaped ratchet wrench having a main body and a force-applying auxiliary arm. The main body includes a cross shaft and a working shaft. A ratchet driving mechanism having a change-over selector is disposed within an intersection position of both shafts. Each end of the cross shaft having an annular groove, and the working shaft has a polygonal head for inserting into a sleeve. Furthermore, the working shaft includes an annular groove in close vicinity to the cross shaft. The force-applying auxiliary arm includes an internal hole for mounting on either end of the working shaft or the cross shaft of the main body. The force-applying auxiliary arm has one end with an engaging socket and another end with a handle portion.

Abstract: The invented method involves one or more gateways sniffing the voice channel during the voice mode. If it is determined that V.8bis signals are being initiated, then the gateway breaks these exchanges by suppressing such signaling, thereby avoiding the above-described detrimental effects. Modem relay communications then are allowed to proceed. Briefly, the method and apparatus involve monitoring a call during a voice mode phase for an initiating signal representative of the defined signaling, the monitoring being performed by a local gateway and, if such an initiating signal is detected during the monitoring, then suppressing such detected signaling in such manner that the signaling does not reach the remote gateway. Preferably, the monitoring is for an initiating signal characterized by a dual tone of defined frequency and duration of approximately 1375 Hz and 2002 Hz for a duration of approximately 400 ms or 285 ms, in agreement with the ITU-T Recommendation V.

Abstract: A T-shaped ratchet wrench having a main body and a force-applying auxiliary arm. The main body includes a cross shaft and a working shaft. A ratchet driving mechanism having a change-over selector is disposed within an intersection position of both shafts. Each end of the cross shaft having an annular groove, and the working shaft has a polygonal head for inserting into a sleeve. Furthermore, the working shaft includes an annular groove in close vicinity to the cross shaft. The force-applying auxiliary arm includes an internal hole for mounting on either end of the working shaft or the cross shaft of the main body. The force-applying auxiliary arm has one end with an engaging socket and another end with a handle portion.