Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.

Abstract: A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.

Abstract: This invention provides a polarization conversion light pipe device suited for LCD- or LCoS-based projection applications. The polarization conversion light pipe device encompasses a light tunnel defined by four side reflection mirrors with a rectangular cross section. The light tunnel has a light entrance face at one end and a light exit face at the other end. A front reflection mirror having an aperture thereon is mounted on the light entrance face. A retardation plate for rotating the direction of an electric field of a polarized light beam is situated in the light tunnel. A polarization beam splitter module is situated between the exit face of the light tunnel and the retardation plate. The polarization beam splitter module has a reflective polarization beam splitting surface that is substantially 45 degree-inclined with respect to one of the side reflection mirrors.

Abstract: An illumination system suited for projection display applications is disclosed. The illumination system according to this invention includes a red light-emitting diode (R-LED) light source array, a green light-emitting diode (G-LED) light source array, and a blue light-emitting diode (B-LED) light source array. In one preferred embodiment, the R/G/B-LED light source arrays are coupled to different sides of an x-cube component. Light beams emanated from respective light source arrays are combined by the x-cube component, thereby generating a white-light source for display purposes.

Abstract: A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid on the floor plan, and the floor plan is divided into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. It is then determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor.

Abstract: A rear projection type television having an improved projection lens system is provided. The projection lens system includes a projection lens with a central light axis at its center that is offset from a reference horizontal line. The offset projection lens projects a central light beam through two reflection mirrors that are not parallel with each other to an image projection surface of a front screen. The image projection surface of a front screen is normal to the horizontal line.

Abstract: A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.

Abstract: A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid on the floor plan, and the floor plan is divided into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. It is then determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: An integrated circuit adapted for ECO and FIB debug comprises: a substrate, a spare cell, a top-layer output terminal pad and a top-layer output terminal pad. The spare cell is disposed in substrate and comprises at least one input terminal and at least one output terminal. The top-layer output terminal pad and the top-layer input terminal pad are disposed in a top metal layer. The top metal layer is disposed over the substrate. The top-layer output terminal pad and the top-layer input terminal pad are electrically coupled to the output terminal and input terminal of the spare cell by a via structure, respectively.

Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.

Abstract: The present invention provides a high definition multimedia interface (HDMI) connector comprising an insulated housing assembly, a metallic housing assembly, a plastic outer shell and a front cover, wherein the insulated housing assembly consists of an insertion portion and a wiring block, and said metallic housing assembly consists of a metallic front shell and a metallic rear shell.

Abstract: An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A method for forming shallow trench isolation (STI) structure including providing a substrate comprising an overlying hardmask layer; patterning the hardmask layer to form a hardmask layer opening for etching a trench through a substrate thickness portion; etching a trench according to the patterned overlying hardmask layer; carrying out a wet chemical oxidizing process to form an oxidized surface portion on the hardmask layer; carrying out a wet chemical etching process to remove at least a portion of the oxidized surface portion to form the hardmask opening having an enlarged width and the trench opening comprising rounded upper corners; and, forming a completed planarized STI structure filled with oxide.

Abstract: A transportation crew dispatch method is disclosed. A plurality of initial samples is generated at first. Each initial sample includes a two dimensional transportation crew dispatch coding table. The initial samples are assigned as parent samples. A sample estimation is performed based on object functions and confinement formulas. By rule of roulette wheel, selection possibilities of chromosomes with superior fitness values are increased. After performing processes of chromosome crossover and mutation responsive to the selection possibilities of single point cutting and double point cutting, a process of sample update is executed by partial gene exchange so as to select preferred samples. The fitness value of each sample is determined from business cost, satisfaction of fairness index, and the disobedient cost of the confinement formulas.

Abstract: A carrier dispatch and transfer method is disclosed, which actuates an optimal carrier dispatch and transfer table for generating elements with a kernel of genetic algorithm by a multi-thread method to search setting confinement conditions and object. A plurality of samples are generated randomly, each including a two dimensional carrier dispatch encoding table. The carrier dispatch encoding table and its transportation duties correspond to chromosomes and genes in a genetic algorithm. The samples are utilized as parent generations for being estimated according to a defined object function and a confinement formula. By rule of roulette wheel, selection possibilities of chromosomes with relative superior fitness values are enhanced. After performing processes of chromosome crossover and mutation, a process of sample update is performed by local gene exchange to select superior samples based on the fitness values.

Abstract: A process for forming a semiconductor device with multiple gate insulator thicknesses, wherein exposed surfaces of a semiconductor substrate are protected during a photoresist stripping procedure, has been developed. After growth of an insulator layer on the entire surface of a semiconductor substrate portions of the insulator layer not covered by a photoresist masking shape are selectively removed. A two step photoresist removal procedure is then employed initiating with an ozone water cycle which partially removes the photoresist shape while forming a thin silicon oxide layer on the portions of bare semiconductor surface. A acid-hydrogen peroxide mixture (SPM), is then used to complete the photoresist removal procedure including removal of photoresist residues, with the thin silicon oxide layer formed during the ozone water cycle protecting the previously bare underlying semiconductor surface.

Abstract: The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for storing a predetermined look-up table; the look-up table comprises plural kinds of edge time duties and the corresponding decoded bit combinations thereof. The counting module is for measuring the edge time duty between high edges and low edges of adjacent pulses of the signal, so as to obtain a first and a second time series. The transform module, according to the look-up table, is for translating the first time series to a first decoded series, and the second time series to a second decoded series. The logic module is for performing a corresponding logic operation on the first and the second decoded series, so as to obtain the decoded bit series.

Abstract: The invention relates to a T-handle ratchet wrench including a lateral bar and a ratchet set. The lateral bar has a hollow connection part located in the center of the lateral bar and used for installing the ratchet set. Two flanks of the lateral bar make up a handgrip, respectively. The top of ratchet set is provided with a rotation button while a vertical bar extends downwardly from the rotation button. At least one of the handgrips includes a pivotal ear with a through hole, and the pivotal ear can be fitted into an insertion slot with a through hole at the free end of the lateral bar. A pivotal pin then passes through the through hole in the pivotal ear and the through hole in the insertion slot. This permits a pivotal movement of the handgrip on the pivotal pin. Accordingly, this configuration will considerably minimize the occupied space in packing, transport, storage and carrying. Particularly, the operators can more easily apply his force on the driver under special operation environments.

Abstract: Managing a multicast conference call includes receiving signals at a local endpoint participating in a multicast conference call with remote endpoints. The signals include a local signal associated with the local endpoint and remote signals, where each remote signal is associated with a remote endpoint. Metric ratings are determined, where each metric rating reflects an importance of a signal. The metric ratings include a local metric rating corresponding to the local signal and remote metric ratings, where each remote metric rating corresponds to a remote signal. The local metric rating and the remote metric ratings are compared, and a subset of signals is selected according to the comparison.